Implement assign statements as BUF_BUILTIN

gates/builtins.v

@@ -0,0 +1,3 @@
+module BUF_BUILTIN (output out, input inp);
+    assign out = inp;
+endmodule

generator.py

@@ -3,9 +3,10 @@
 from jinja2 import Template
 from sg_parser import load_sg
 from lib_parser import load_lib
+from lib_parser import merge_libs
+from lib_parser import builtins_lib
 from collections import defaultdict
 from verilog_parser import load_verilog
-from lib_parser import merge_libs
 
 import os
 import re
@@ -93,7 +94,8 @@ def main():
 
     output_dir = "generated"
 
-    lib     = load_lib("libraries/workcraft.lib")
+    lib_wk  = load_lib("libraries/workcraft.lib")
+    lib     = merge_libs(lib_wk, builtins_lib)
     spec    = load_sg("examples/SRAM-master/spec.sg")
     circuit = load_verilog("examples/SRAM-master/circuit.v")
 

lib_parser.py

@@ -3,10 +3,9 @@
 
 
 builtins_lib = {
-    "*assign": {
+    "BUF_BUILTIN": {
         "type": "GATE",
         "state_input": None,
-        "name": "*assign",
         "output": "out",
         "inputs": ["inp"],
         "definition": "out=inp",

templates/circuit.v

@@ -61,7 +61,7 @@ module circuit (
 		{%- set pin_net = output_pre if pin==output_pin else net -%}
 		.{{pin}}({{pin_net}}){{ ", " if not loop.last }}
 		{%- endfor -%}
-	);
+	); {{"// virtual module" if mod.get("virtual")}}
 
 	DFF {{instance}}_ff (
 		.CK(clk),

verilog_parser.py

@@ -81,11 +81,12 @@ def add_assign(circuit, out, inp):
     # prefixed with * to make them non-compliant with the Verilog standard (and
     # thus obviously in need of special treatment).
 
-    instance = "*%s" % out
+    instance = "ASSIGN_%s" % out
 
     circuit["modules"][instance] = {
-        "type": "*assign",
-        "connections": { "inp": inp, "out": out }
+        "type": "BUF_BUILTIN",
+        "connections": { "inp": inp, "out": out },
+        "virtual": True
     }