riscv-mini use makefile to trigger full test

ucsc-vama · Jan 31, 2023 · 8a6793a · 8a6793a
1 parent d29a0a4
commit 8a6793a
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Showing 2 changed files with 19 additions and 2 deletions.
diff --git a/riscv-mini/.gitignore b/riscv-mini/.gitignore
@@ -0,0 +1,5 @@
+top
+Tile.h
+Tile.fir
+test-*
+VTile
diff --git a/riscv-mini/Makefile b/riscv-mini/Makefile
@@ -2,16 +2,16 @@
 generated_dir = $(abspath riscv-mini/generated-src)
 fir_filename = Tile.fir
 fir_path = $(abspath $(fir_filename))
+
 riscv-mini/README.md:
 	git submodule update --init riscv-mini
 
 $(generated_dir)/$(fir_filename): riscv-mini/README.md
-	cd riscv-mini; make compile 
+	cd riscv-mini; make compile
 
 $(fir_filename): $(generated_dir)/$(fir_filename)
 	cp $(generated_dir)/$(fir_filename) .
 
-
 Tile.h: $(fir_filename)
 	cd ../essent; sbt 'run -O2 $(fir_path)'
 
@@ -20,3 +20,15 @@ INCLUDES = -I../firrtl-sig
 
 top: top.cc mm.cc mm.h Tile.h
 	$(CXX) $(CXXFLAGS) $(INCLUDES) top.cc mm.cc -o top 
+
+.PHONY: clean
+clean:
+	rm -rf $(fir_filename) Tile.h top VTile test-*
+
+VTile: riscv-mini/README.md
+	cd riscv-mini; make verilator
+	cp riscv-mini/VTile .
+
+.PHONY: test
+test: top VTile
+	./test.sh