Merge pull request #1 from vyoma-systems/misalign

fix:added misaligned test for ld and sd
vyoma-systems · Apr 16, 2024 · 5958155 · 5958155
2 parents ce8bd9a + c6806ab
commit 5958155
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diff --git a/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-ld-01.S b/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-ld-01.S
@@ -0,0 +1,169 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.12.1
+// timestamp : Tue Apr  9 07:15:34 2024 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /home/vsysuser/verif/final_cut/zilsd/wd/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/vsysuser/verif/final_cut/zilsd/wd/riscv-ctg/sample_cgfs/rv32zilsd_priv.cgf \
+ \
+//                  -- xlen 32  \
+//                  --randomize \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the ldz instruction of the RISC-V RV32Zilsd extension for the misalign-ld covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32IZilsd")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True;def TEST_CASE_1=True;",misalign-ld)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-ld)
+
+RVTEST_SIGBASE(x1,signature_x1_1)
+
+inst_0:
+// rs1==x28, rd==x2, ea_align == 1, 
+// opcode:$opcode op1:x28; dest:x2; immval:0x2; align:1;rd_hi:x3
+TEST_LOAD_ZILSD(x1,x7,0,x28,x2,x3,0x2,0*XLEN/8,ld,1)
+
+inst_1:
+// rs1==x14, rd==x26, ea_align == 2, 
+// opcode:$opcode op1:x14; dest:x26; immval:0x40; align:2;rd_hi:x27
+TEST_LOAD_ZILSD(x1,x7,0,x14,x26,x27,0x40,2*XLEN/8,ld,2)
+
+inst_2:
+// rs1==x12, rd==x4, ea_align == 3, 
+// opcode:$opcode op1:x12; dest:x4; immval:-0x41; align:3;rd_hi:x5
+TEST_LOAD_ZILSD(x1,x7,0,x12,x4,x5,-0x41,4*XLEN/8,ld,3)
+
+inst_3:
+// rs1==x22, rd==x24, ea_align == 4, 
+// opcode:$opcode op1:x22; dest:x24; immval:-0x3; align:4;rd_hi:x25
+TEST_LOAD_ZILSD(x1,x7,0,x22,x24,x25,-0x3,6*XLEN/8,ld,4)
+
+inst_4:
+// rs1==x20, rd==x10, ea_align == 5, 
+// opcode:$opcode op1:x20; dest:x10; immval:0x5; align:5;rd_hi:x11
+TEST_LOAD_ZILSD(x1,x7,0,x20,x10,x11,0x5,8*XLEN/8,ld,5)
+
+inst_5:
+// rs1==x2, rd==x16, ea_align == 6, 
+// opcode:$opcode op1:x2; dest:x16; immval:-0x21; align:6;rd_hi:x17
+TEST_LOAD_ZILSD(x1,x7,0,x2,x16,x17,-0x21,10*XLEN/8,ld,6)
+
+inst_6:
+// rs1==x30, rd==x20, ea_align == 7, 
+// opcode:$opcode op1:x30; dest:x20; immval:-0x9; align:7;rd_hi:x21
+TEST_LOAD_ZILSD(x1,x7,0,x30,x20,x21,-0x9,12*XLEN/8,ld,7)
+
+inst_7:
+// rs1==x24, rd==x18, 
+// opcode:$opcode op1:x24; dest:x18; immval:-0x800; align:0;rd_hi:x19
+TEST_LOAD_ZILSD(x1,x7,0,x24,x18,x19,-0x800,14*XLEN/8,ld,0)
+
+inst_8:
+// rs1==x10, rd==x28, 
+// opcode:$opcode op1:x10; dest:x28; immval:-0x800; align:0;rd_hi:x29
+TEST_LOAD_ZILSD(x1,x7,0,x10,x28,x29,-0x800,16*XLEN/8,ld,0)
+
+inst_9:
+// rs1==x6, rd==x8, 
+// opcode:$opcode op1:x6; dest:x8; immval:-0x800; align:0;rd_hi:x9
+TEST_LOAD_ZILSD(x1,x7,0,x6,x8,x9,-0x800,18*XLEN/8,ld,0)
+
+inst_10:
+// rs1==x4, rd==x30, 
+// opcode:$opcode op1:x4; dest:x30; immval:-0x800; align:0;rd_hi:x31
+TEST_LOAD_ZILSD(x1,x7,0,x4,x30,x31,-0x800,20*XLEN/8,ld,0)
+
+inst_11:
+// rs1==x26, rd==x6, 
+// opcode:$opcode op1:x26; dest:x6; immval:-0x800; align:0;rd_hi:x7
+TEST_LOAD_ZILSD(x1,x7,0,x26,x6,x7,-0x800,22*XLEN/8,ld,0)
+RVTEST_SIGBASE(x1,signature_x1_2)
+
+inst_12:
+// rs1==x18, rd==x12, 
+// opcode:$opcode op1:x18; dest:x12; immval:-0x800; align:0;rd_hi:x13
+TEST_LOAD_ZILSD(x1,x7,0,x18,x12,x13,-0x800,0*XLEN/8,ld,0)
+
+inst_13:
+// rs1==x16, rd==x22, 
+// opcode:$opcode op1:x16; dest:x22; immval:-0x800; align:0;rd_hi:x23
+TEST_LOAD_ZILSD(x1,x7,0,x16,x22,x23,-0x800,2*XLEN/8,ld,0)
+
+inst_14:
+// rs1==x8, rd==x14, 
+// opcode:$opcode op1:x8; dest:x14; immval:-0x800; align:0;rd_hi:x15
+TEST_LOAD_ZILSD(x1,x7,0,x8,x14,x15,-0x800,4*XLEN/8,ld,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+
+
+signature_x1_0:
+    .fill 0*((XLEN/8)/4),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 24*((XLEN/8)/4),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 6*((XLEN/8)/4),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+tsig_begin_canary:
+CANARY;
+
+mtrap_sigptr:
+    .fill 64*XLEN/32,4,0xdeadbeef
+
+tsig_end_canary:
+CANARY;
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*XLEN/32,4,0xdeadbeef
+
+#endif
+
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END
diff --git a/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-sd-o1.S b/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-sd-o1.S
@@ -0,0 +1,169 @@
+
+// -----------
+// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
+// version   : 0.12.1
+// timestamp : Tue Apr  9 07:15:34 2024 GMT
+// usage     : riscv_ctg \
+//                  -- cgf //                  --cgf /home/vsysuser/verif/final_cut/zilsd/wd/riscv-ctg/sample_cgfs/dataset.cgf \
+//                  --cgf /home/vsysuser/verif/final_cut/zilsd/wd/riscv-ctg/sample_cgfs/rv32zilsd_priv.cgf \
+ \
+//                  -- xlen 32  \
+//                  --randomize \
+// -----------
+//
+// -----------
+// Copyright (c) 2020. RISC-V International. All rights reserved.
+// SPDX-License-Identifier: BSD-3-Clause
+// -----------
+//
+// This assembly file tests the sdz instruction of the RISC-V RV32Zilsd extension for the misalign-sd covergroup.
+// 
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32IZilsd")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True;def TEST_CASE_1=True;",misalign-sd)
+
+RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-sd)
+
+RVTEST_SIGBASE(x1,signature_x1_1)
+
+inst_0:
+// rs1==x4, rs2==x28, ea_align == 1, 
+// opcode:$opcode; op1:x4; op2:x28; op2val:-0x2;op3val:0x800000; immval:0x3ff; align:1; rs2_hi:x29
+TEST_STORE_ZILSD(x1,x5,0,x4,x28,x29,-0x2,0x800000,0x3ff,0*XLEN/8,sd,1)
+
+inst_1:
+// rs1==x18, rs2==x10, ea_align == 2, 
+// opcode:$opcode; op1:x18; op2:x10; op2val:0x4000000;op3val:-0x100001; immval:-0x400; align:2; rs2_hi:x11
+TEST_STORE_ZILSD(x1,x5,0,x18,x10,x11,0x4000000,-0x100001,-0x400,2*XLEN/8,sd,2)
+
+inst_2:
+// rs1==x12, rs2==x6, ea_align == 3, 
+// opcode:$opcode; op1:x12; op2:x6; op2val:-0x21;op3val:0x800000; immval:0x6; align:3; rs2_hi:x7
+TEST_STORE_ZILSD(x1,x5,0,x12,x6,x7,-0x21,0x800000,0x6,4*XLEN/8,sd,3)
+
+inst_3:
+// rs1==x22, rs2==x4, ea_align == 4, 
+// opcode:$opcode; op1:x22; op2:x4; op2val:0x6;op3val:-0x6; immval:0x8; align:4; rs2_hi:x5
+TEST_STORE_ZILSD(x1,x5,0,x22,x4,x5,0x6,-0x6,0x8,6*XLEN/8,sd,4)
+
+inst_4:
+// rs1==x6, rs2==x2, ea_align == 5, 
+// opcode:$opcode; op1:x6; op2:x2; op2val:0x3fffffff;op3val:-0x2000001; immval:-0x21; align:5; rs2_hi:x3
+TEST_STORE_ZILSD(x1,x5,0,x6,x2,x3,0x3fffffff,-0x2000001,-0x21,8*XLEN/8,sd,5)
+
+inst_5:
+// rs1==x14, rs2==x24, ea_align == 6, 
+// opcode:$opcode; op1:x14; op2:x24; op2val:0x4000000;op3val:0x10000000; immval:0x400; align:6; rs2_hi:x25
+TEST_STORE_ZILSD(x1,x5,0,x14,x24,x25,0x4000000,0x10000000,0x400,10*XLEN/8,sd,6)
+
+inst_6:
+// rs1==x26, rs2==x18, ea_align == 7, 
+// opcode:$opcode; op1:x26; op2:x18; op2val:-0x400001;op3val:-0x1000001; immval:-0x11; align:7; rs2_hi:x19
+TEST_STORE_ZILSD(x1,x5,0,x26,x18,x19,-0x400001,-0x1000001,-0x11,12*XLEN/8,sd,7)
+
+inst_7:
+// rs1==x16, rs2==x8, 
+// opcode:$opcode; op1:x16; op2:x8; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x9
+TEST_STORE_ZILSD(x1,x5,0,x16,x8,x9,-0x80000000,-0x80000000,-0x800,14*XLEN/8,sd,0)
+
+inst_8:
+// rs1==x8, rs2==x12, 
+// opcode:$opcode; op1:x8; op2:x12; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x13
+TEST_STORE_ZILSD(x1,x5,0,x8,x12,x13,-0x80000000,-0x80000000,-0x800,16*XLEN/8,sd,0)
+
+inst_9:
+// rs1==x10, rs2==x20, 
+// opcode:$opcode; op1:x10; op2:x20; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x21
+TEST_STORE_ZILSD(x1,x5,0,x10,x20,x21,-0x80000000,-0x80000000,-0x800,18*XLEN/8,sd,0)
+
+inst_10:
+// rs1==x28, rs2==x30, 
+// opcode:$opcode; op1:x28; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31
+TEST_STORE_ZILSD(x1,x5,0,x28,x30,x31,-0x80000000,-0x80000000,-0x800,20*XLEN/8,sd,0)
+
+inst_11:
+// rs1==x2, rs2==x22, 
+// opcode:$opcode; op1:x2; op2:x22; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x23
+TEST_STORE_ZILSD(x1,x5,0,x2,x22,x23,-0x80000000,-0x80000000,-0x800,22*XLEN/8,sd,0)
+RVTEST_SIGBASE(x1,signature_x1_2)
+
+inst_12:
+// rs1==x20, rs2==x16, 
+// opcode:$opcode; op1:x20; op2:x16; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x17
+TEST_STORE_ZILSD(x1,x5,0,x20,x16,x17,-0x80000000,-0x80000000,-0x800,0*XLEN/8,sd,0)
+
+inst_13:
+// rs1==x30, rs2==x14, 
+// opcode:$opcode; op1:x30; op2:x14; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x15
+TEST_STORE_ZILSD(x1,x5,0,x30,x14,x15,-0x80000000,-0x80000000,-0x800,2*XLEN/8,sd,0)
+
+inst_14:
+// rs1==x24, rs2==x26, 
+// opcode:$opcode; op1:x24; op2:x26; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x27
+TEST_STORE_ZILSD(x1,x5,0,x24,x26,x27,-0x80000000,-0x80000000,-0x800,4*XLEN/8,sd,0)
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 4
+rvtest_data:
+.word 0xbabecafe
+.word 0xabecafeb
+.word 0xbecafeba
+.word 0xecafebab
+RVTEST_DATA_END
+
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+
+
+
+signature_x1_0:
+    .fill 0*((XLEN/8)/4),4,0xdeadbeef
+
+
+signature_x1_1:
+    .fill 24*((XLEN/8)/4),4,0xdeadbeef
+
+
+signature_x1_2:
+    .fill 6*((XLEN/8)/4),4,0xdeadbeef
+
+#ifdef rvtest_mtrap_routine
+tsig_begin_canary:
+CANARY;
+
+mtrap_sigptr:
+    .fill 64*XLEN/32,4,0xdeadbeef
+
+tsig_end_canary:
+CANARY;
+#endif
+
+#ifdef rvtest_gpr_save
+
+gpr_save:
+    .fill 32*XLEN/32,4,0xdeadbeef
+
+#endif
+
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END