> generate verilog

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wele0612 · Jan 30, 2024 · 3c583ad · 3c583ad
1 parent 5a52c17
commit 3c583ad
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Showing 3 changed files with 2 additions and 71 deletions.
diff --git a/npc/playground/src/DecoupledGCD.scala b/npc/playground/src/DecoupledGCD.scala
diff --git a/npc/playground/src/Elaborate.scala b/npc/playground/src/Elaborate.scala
@@ -1,7 +1,7 @@
 import circt.stage._
 
 object Elaborate extends App {
-  def top = new GCD()
+  def top = new Top_Module()
   val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
   (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
 }
diff --git a/npc/playground/src/GCD.scala → npc/playground/src/Top_Module.scala b/npc/playground/src/GCD.scala → npc/playground/src/Top_Module.scala
@@ -5,7 +5,7 @@ import chisel3._
   * Subtracts the smaller from the larger until register y is zero.
   * value in register x is then the GCD
   */
-class GCD extends Module {
+class Top_Module extends Module {
   val io = IO(new Bundle {
     val value1        = Input(UInt(16.W))
     val value2        = Input(UInt(16.W))