> generate verilog

ysyx_23060173 薛立伟
Linux tianyi-virtual-machine 6.5.0-15-generic OSCPU#15~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Fri Jan 12 18:54:30 UTC 2 x86_64 x86_64 x86_64 GNU/Linux
 10:46:31 up 45 min,  1 user,  load average: 1.33, 1.30, 1.26

npc/Makefile

@@ -17,7 +17,7 @@ NVBOARD_INC = $(NVBOARD_HOME)/include
 
 nvboard: verilog $(VSRCS) $(CSRCS)
 	verilator $(VERILATOR_CFLAGS) \
-		--top-module $(TOP_NAME) $^ \
+		--top-module $(TOP_NAME) $(VSRCS) $(CSRCS) \
 		$(addprefix -CFLAGS , $(CXXFLAGS)) $(addprefix -LDFLAGS , $(LDFLAGS)) \
 		--Mdir $(OBJ_DIR) --exe -o $(abspath $(BIN))