> generate verilog

薛立伟 Linux tianyi-virtual-machine 6.5.0-15-generic OSCPU#15~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Fri Jan 12 18:54:30 UTC 2 x86_64 x86_64 x86_64 GNU/Linux 22:16:50 up 1:41, 1 user, load average: 0.86, 0.90, 0.81
wele0612 · Jan 30, 2024 · 8ba3dd2 · 8ba3dd2
1 parent 193e2aa
commit 8ba3dd2
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/npc/playground/src/Top_Module.scala b/npc/playground/src/Top_Module.scala
@@ -4,11 +4,13 @@ import chisel3._
  * Bundle for nvboard
   */
 class NVboard_IOs extends Bundle{
-  val ledr=Output(VecInit(Seq.fill(16)(false.B)))
+  val ledr=Output(Vec(16,Bool()))
 }
 class Top_Module extends Module {
   val io=IO(new NVboard_IOs)
 
+  io.ledr:=0.U.asTypeOf(io.ledr)
+
   io.ledr(0):=true.B
   io.ledr(1):=false.B
 }