> generate verilog

薛立伟 Linux tianyi-virtual-machine 6.5.0-15-generic OSCPU#15~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Fri Jan 12 18:54:30 UTC 2 x86_64 x86_64 x86_64 GNU/Linux 21:10:33 up 35 min, 1 user, load average: 0.91, 0.52, 0.39
wele0612 · Jan 30, 2024 · dada16d · dada16d
1 parent 30f5d66
commit dada16d
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/npc/playground/test/src/TopSpec.scala b/npc/playground/test/src/TopSpec.scala
@@ -17,6 +17,7 @@ import utest._
   */
 
 object TopSpec extends ChiselUtestTester {
+  val name="Top module test"
   /*
   val tests = Tests {
     test("GCD") {