drivers: uart: microchip: add support for mec15xx

update uart mchp xec driver to support mec15xx and add pinctrl support for mec15xx uart Signed-off-by: Jay Vasanth <[email protected]>
zephyrproject-rtos · Oct 4, 2022 · f6e2cb9 · f6e2cb9
1 parent a657aba
commit f6e2cb9
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Showing 4 changed files with 71 additions and 17 deletions.
diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts
@@ -52,6 +52,8 @@
 &uart1 {
 	status = "okay";
 	current-speed = <115200>;
+	pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
+	pinctrl-names = "default";
 };
 
 &adc0 {

diff --git a/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853.dts
@@ -80,6 +80,8 @@
 &uart2 {
 	status = "okay";
 	current-speed = <115200>;
+	pinctrl-0 = <&uart2_tx_gpio146 &uart2_rx_gpio145>;
+	pinctrl-names = "default";
 };
 
 &adc0 {

diff --git a/drivers/serial/uart_mchp_xec.c b/drivers/serial/uart_mchp_xec.c
@@ -24,16 +24,15 @@
 #include <zephyr/init.h>
 #include <zephyr/toolchain.h>
 #include <zephyr/linker/sections.h>
+#ifdef CONFIG_SOC_SERIES_MEC172X
 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
 #include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
+#endif
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/uart.h>
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/spinlock.h>
 
-BUILD_ASSERT(IS_ENABLED(CONFIG_SOC_SERIES_MEC172X),
-	     "XEC UART driver only support MEC172x at this time");
-
 /* Clock source is 1.8432 MHz derived from PLL 48 MHz */
 #define XEC_UART_CLK_SRC_1P8M		0
 /* Clock source is PLL 48 MHz output */
@@ -195,6 +194,56 @@ struct uart_xec_dev_data {
 
 static const struct uart_driver_api uart_xec_driver_api;
 
+#ifdef CONFIG_SOC_SERIES_MEC172X
+
+static void uart_clr_slp_en(const struct device *dev)
+{
+	struct uart_xec_device_config const *dev_cfg = dev->config;
+
+	z_mchp_xec_pcr_periph_sleep(dev_cfg->pcr_idx, dev_cfg->pcr_bitpos, 0);
+}
+
+static inline void uart_xec_girq_clr(const struct device *dev)
+{
+	struct uart_xec_device_config const *dev_cfg = dev->config;
+
+	mchp_soc_ecia_girq_src_clr(dev_cfg->girq_id, dev_cfg->girq_pos);
+}
+
+static inline void uart_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
+{
+	mchp_xec_ecia_girq_src_en(girq_idx, girq_posn);
+}
+
+#else
+
+static void uart_clr_slp_en(const struct device *dev)
+{
+	struct uart_xec_device_config const *dev_cfg = dev->config;
+
+	if (dev_cfg->pcr_bitpos == MCHP_PCR2_UART0_POS) {
+		mchp_pcr_periph_slp_ctrl(PCR_UART0, 0);
+	} else if (dev_cfg->pcr_bitpos == MCHP_PCR2_UART1_POS) {
+		mchp_pcr_periph_slp_ctrl(PCR_UART1, 0);
+	} else {
+		mchp_pcr_periph_slp_ctrl(PCR_UART2, 0);
+	}
+}
+
+static inline void uart_xec_girq_clr(const struct device *dev)
+{
+	struct uart_xec_device_config const *dev_cfg = dev->config;
+
+	MCHP_GIRQ_SRC(dev_cfg->girq_id) = BIT(dev_cfg->girq_pos);
+}
+
+static inline void uart_xec_girq_en(uint8_t girq_idx, uint8_t girq_posn)
+{
+	MCHP_GIRQ_ENSET(girq_idx) = BIT(girq_posn);
+}
+
+#endif
+
 static void set_baud_rate(const struct device *dev, uint32_t baud_rate)
 {
 	const struct uart_xec_device_config * const dev_cfg = dev->config;
@@ -363,11 +412,7 @@ static int uart_xec_init(const struct device *dev)
 	struct uart_xec_dev_data *dev_data = dev->data;
 	int ret;
 
-	ret = z_mchp_xec_pcr_periph_sleep(dev_cfg->pcr_idx,
-					  dev_cfg->pcr_bitpos, 0);
-	if (ret != 0) {
-		return ret;
-	}
+	uart_clr_slp_en(dev);
 
 	ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
 	if (ret != 0) {
@@ -750,15 +795,14 @@ static void uart_xec_irq_callback_set(const struct device *dev,
  */
 static void uart_xec_isr(const struct device *dev)
 {
-	const struct uart_xec_device_config * const dev_cfg = dev->config;
 	struct uart_xec_dev_data * const dev_data = dev->data;
 
 	if (dev_data->cb) {
 		dev_data->cb(dev, dev_data->cb_data);
 	}
 
 	/* clear ECIA GIRQ R/W1C status bit after UART status cleared */
-	mchp_xec_ecia_girq_src_clr(dev_cfg->girq_id, dev_cfg->girq_pos);
+	uart_xec_girq_clr(dev);
 }
 
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
@@ -862,7 +906,7 @@ static const struct uart_driver_api uart_xec_driver_api = {
 			    uart_xec_isr, DEVICE_DT_INST_GET(n),	\
 			    0);						\
 		irq_enable(DT_INST_IRQN(n));				\
-		mchp_xec_ecia_girq_src_en(DT_INST_PROP_BY_IDX(n, girqs, 0), \
+		uart_xec_girq_en(DT_INST_PROP_BY_IDX(n, girqs, 0), \
 					  DT_INST_PROP_BY_IDX(n, girqs, 1)); \
 	}
 #else

diff --git a/dts/arm/microchip/mec1501hsz.dtsi b/dts/arm/microchip/mec1501hsz.dtsi
@@ -162,30 +162,36 @@
 			pcrs = <1 9>;
 		};
 		uart0: uart@400f2400 {
-			compatible = "ns16550";
+			compatible = "microchip,xec-uart";
 			reg = <0x400f2400 0x400>;
 			interrupts = <40 0>;
 			clock-frequency = <1843200>;
 			current-speed = <38400>;
-			reg-shift = <0>;
+			girqs = <15 0>;
+			pcrs = <2 1>;
+			ldn = <9>;
 			status = "disabled";
 		};
 		uart1: uart@400f2800 {
-			compatible = "ns16550";
+			compatible = "microchip,xec-uart";
 			reg = <0x400f2800 0x400>;
 			interrupts = <41 0>;
 			clock-frequency = <1843200>;
 			current-speed = <38400>;
-			reg-shift = <0>;
+			girqs = <15 1>;
+			pcrs = <2 2>;
+			ldn = <10>;
 			status = "disabled";
 		};
 		uart2: uart@400f2c00 {
-			compatible = "ns16550";
+			compatible = "microchip,xec-uart";
 			reg = <0x400f2c00 0x400>;
 			interrupts = <44 0>;
 			clock-frequency = <1843200>;
 			current-speed = <38400>;
-			reg-shift = <0>;
+			girqs = <15 4>;
+			pcrs = <2 28>;
+			ldn = <11>;
 			status = "disabled";
 		};