64 bit race on timer counter in cavs_timer

[andyross]

The CAVS hardware has a 64 bit timer counter (it's the same device as the HD Audio wall clock timer). But the code to read it looks like this:

static uint64_t count(void)
{
	return shim_regs->walclk;
}

When compiled on Xtensa, this produces two sequential 32 bit reads of the value. And that's wrong, because the hardware continues to run. It's possible for the two reads to straddle a rollover of the low word and increment of the high word.

This needs to be fixed to be safe. The simplest scheme is to read the high word twice, compare the two values, and repeat the process if they don't match.

[andyross]

Discovered via conversation with @lgirdwood and @lyakh who had tripped over the same bug in upstream (non-Zephyr) SOF code. We have exactly the same messup.

[lgirdwood]

@andyross fell free to copy and paste from SOF once it merged and passes QA and validation.