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spi: stm32f0 IRQ priority is invalid #6238

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dwagenk opened this issue Feb 16, 2018 · 0 comments
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spi: stm32f0 IRQ priority is invalid #6238

dwagenk opened this issue Feb 16, 2018 · 0 comments
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dwagenk commented Feb 16, 2018

Executing spi_loopback test for f0 based boards (stm32f072b_disco) with assertions enabled fails:

ASSERTION FAIL [prio <= ((1 << 2) - 1)] @ /home/dw_dev/0_zephyr/arch/arm/core/irq_manage.c:115:
        invalid priority 5! values must be less than 4

in dts/arm/st/stm32f0.dtsi interrupt priority is set to 5, but should be lower for f0 series.
@nashif nashif added the bug The issue is a bug, or the PR is fixing a bug label Feb 16, 2018
ydamigos added a commit to ydamigos/zephyr that referenced this issue Feb 17, 2018
@ydamigos
dts/arm/st: Fix SPI1 interrupt priority for STM32f0
98cbff3 
STM32F0 family has only 2 interrupt priority bits.

Fixes zephyrproject-rtos#6238

Signed-off-by: Yannis Damigos <[email protected]>
@ydamigos ydamigos mentioned this issue Feb 17, 2018
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@ydamigos ydamigos self-assigned this Feb 17, 2018
This was referenced Feb 17, 2018
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@galak galak closed this as completed in 306298e Feb 20, 2018
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