arc: hsdk: bug fixes and new feature supports

CODEOWNERS

@@ -139,6 +139,7 @@
 /drivers/modem/                           @mike-scott
 /drivers/pcie/                            @gnuless
 /drivers/pinmux/stm32/                    @rsalveti @idlethread
+/drivers/pinmux/*hsdk*                    @iriszzw
 /drivers/sensor/                          @MaureenHelm
 /drivers/sensor/ams_iAQcore/              @alexanderwachter
 /drivers/sensor/ens210/                   @alexanderwachter

arch/arc/core/arc_connect.c

@@ -349,7 +349,7 @@ u32_t z_arc_connect_idu_read_mode(u32_t irq_num)
 void z_arc_connect_idu_set_dest(u32_t irq_num, u32_t core_mask)
 {
 	LOCKED(&arc_connect_spinlock) {
-		z_arc_connect_cmd_data(ARC_CONNECT_CMD_IDU_SET_MODE,
+		z_arc_connect_cmd_data(ARC_CONNECT_CMD_IDU_SET_DEST,
 			irq_num, core_mask);
 	}
 }

boards/arc/hsdk/CMakeLists.txt

@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources_ifdef(CONFIG_PINMUX_HSDK pinmux.c)

boards/arc/hsdk/Kconfig.defconfig

@@ -8,4 +8,47 @@ if BOARD_HSDK
 config BOARD
 	default "hsdk"
 
+if GPIO
+
+config GPIO_DW
+	default y
+
+if GPIO_DW
+
+config GPIO_DW_0
+	default y
+
+endif # GPIO_DW
+
+endif # GPIO
+
+if SPI
+
+config SPI_DW
+	default y
+
+if SPI_DW
+
+config SPI_DW_FIFO_DEPTH
+	default 32
+
+config SPI_DW_ARC_AUX_REGS
+	default n
+
+config SPI_DW_ACCESS_WORD_ONLY
+	default y
+
+config SPI_0
+	default y
+
+config SPI_1
+	default y
+
+config SPI_2
+	default y
+
+endif # SPI_DW
+
+endif # SPI
+
 endif # BOARD_HSDK

boards/arc/hsdk/hsdk.dts

@@ -27,3 +27,23 @@
 	status = "okay";
 	current-speed = <115200>;
 };
+
+&gpio0 {
+	status = "okay";
+	interrupts = <56 1>;
+};
+
+&spi0 {
+	status = "okay";
+	clock-frequency = <33333333>;
+};
+
+&spi1 {
+	status = "okay";
+	clock-frequency = <33333333>;
+};
+
+&spi2 {
+	status = "okay";
+	clock-frequency = <33333333>;
+};

boards/arc/hsdk/hsdk_defconfig

@@ -13,3 +13,7 @@ CONFIG_ARCV2_TIMER=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
+CONFIG_PINMUX=y
+CONFIG_PINMUX_HSDK=y
+CONFIG_GPIO=y
+CONFIG_SPI=y

boards/arc/hsdk/pinmux.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2019 Synopsys
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <init.h>
+#include <drivers/pinmux.h>
+
+static int board_pinmux_init(struct device *device)
+{
+	ARG_UNUSED(device);
+
+	struct device *pinmux = device_get_binding(CONFIG_PINMUX_NAME);
+
+	if (pinmux == NULL) {
+		return -ENXIO;
+	}
+	/*
+	 * to do configuration for each sel,
+	 * please refer the doc for hsdk board.
+	 */
+	pinmux_pin_set(pinmux, HSDK_PINMUX_SEL0, HSDK_PINMUX_FUN0);
+	pinmux_pin_set(pinmux, HSDK_PINMUX_SEL1, HSDK_PINMUX_FUN0);
+	pinmux_pin_set(pinmux, HSDK_PINMUX_SEL2, HSDK_PINMUX_FUN0);
+	pinmux_pin_set(pinmux, HSDK_PINMUX_SEL3, HSDK_PINMUX_FUN2);
+	pinmux_pin_set(pinmux, HSDK_PINMUX_SEL4, HSDK_PINMUX_FUN0);
+	pinmux_pin_set(pinmux, HSDK_PINMUX_SEL5, HSDK_PINMUX_FUN0);
+	pinmux_pin_set(pinmux, HSDK_PINMUX_SEL6, HSDK_PINMUX_FUN0);
+	pinmux_pin_set(pinmux, HSDK_PINMUX_SEL7, HSDK_PINMUX_FUN0);
+
+	return 0;
+}
+
+
+SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY);

drivers/pinmux/CMakeLists.txt

@@ -13,3 +13,4 @@ zephyr_sources_ifdef(CONFIG_PINMUX_STM32           stm32/pinmux_stm32.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_SAM0            pinmux_sam0.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_INTEL_S1000     pinmux_intel_s1000.c)
 zephyr_sources_ifdef(CONFIG_PINMUX_RV32M1          pinmux_rv32m1.c)
+zephyr_sources_ifdef(CONFIG_PINMUX_HSDK            pinmux_hsdk.c)

drivers/pinmux/Kconfig

@@ -63,4 +63,6 @@ source "drivers/pinmux/Kconfig.rv32m1"
 
 source "drivers/pinmux/Kconfig.xec"
 
+source "drivers/pinmux/Kconfig.hsdk"
+
 endif # PINMUX

drivers/pinmux/Kconfig.hsdk

@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+menuconfig PINMUX_HSDK
+	bool "ARC HSDK I/O pin mux driver"
+	depends on SOC_ARC_HSDK
+	help
+	  Enable driver for ARC HSDK I/O pin mux.

drivers/pinmux/pinmux_hsdk.c

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2019 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <device.h>
+#include <drivers/pinmux.h>
+#include <soc.h>
+
+#define creg_gpio_mux_reg	(*(volatile u32_t *)CREG_GPIO_MUX_BASE_ADDR)
+
+void _arc_sync(void)
+{
+	__asm__ volatile("sync");
+}
+
+static int pinmux_hsdk_set(struct device *dev, u32_t pin, u32_t func)
+{
+
+	if (func >= HSDK_PINMUX_FUNS || pin >= HSDK_PINMUX_SELS)
+		return -EINVAL;
+
+	creg_gpio_mux_reg &= ~(0x07U << (pin * 3));
+	creg_gpio_mux_reg |= (func << (pin * 3));
+
+	_arc_sync();
+
+	return 0;
+}
+
+static int pinmux_hsdk_get(struct device *dev, u32_t pin, u32_t *func)
+{
+
+	if (pin >= HSDK_PINMUX_SELS || func == NULL)
+		return -EINVAL;
+
+	*func = (creg_gpio_mux_reg >> (pin * 3)) & 0x07U;
+
+	return 0;
+}
+
+static int pinmux_hsdk_pullup(struct device *dev, u32_t pin, u8_t func)
+{
+	return -ENOTSUP;
+}
+
+static int pinmux_hsdk_input(struct device *dev, u32_t pin, u8_t func)
+{
+	return -ENOTSUP;
+}
+
+static int pinmux_hsdk_init(struct device *dev)
+{
+	ARG_UNUSED(dev);
+	return 0;
+}
+
+static const struct pinmux_driver_api pinmux_hsdk_driver_api = {
+	.set = pinmux_hsdk_set,
+	.get = pinmux_hsdk_get,
+	.pullup = pinmux_hsdk_pullup,
+	.input = pinmux_hsdk_input,
+};
+
+DEVICE_AND_API_INIT(pinmux_hsdk, CONFIG_PINMUX_NAME,
+			&pinmux_hsdk_init, NULL, NULL,
+			PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
+			&pinmux_hsdk_driver_api);

drivers/spi/Kconfig.dw

@@ -35,6 +35,15 @@ config SPI_DW_FIFO_DEPTH
 	  SSI_RX_FIFO_DEPTH of the DesignWare Synchronous
 	  Serial Interface. Depth ranges from 2-256.
 
+config SPI_DW_ACCESS_WORD_ONLY
+	bool "DesignWare SPI only allows word access"
+	default n
+	depends on SPI_DW
+	help
+	  In some case, e.g. ARC HS Development kit, the peripheral space of
+	  DesignWare SPI only allows word access, byte access will raise
+	  exception.
+
 if SPI_0
 
 config SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE

drivers/spi/spi_dw.h

@@ -206,12 +206,21 @@ struct spi_dw_data {
 #define z_extra_clock_off(...)
 
 /* Based on those macros above, here are common helpers for some registers */
-DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16)
+
 DEFINE_MM_REG_READ(txflr, DW_SPI_REG_TXFLR, 32)
 DEFINE_MM_REG_READ(rxflr, DW_SPI_REG_RXFLR, 32)
+
+#ifdef CONFIG_SPI_DW_ACCESS_WORD_ONLY
+DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 32)
+DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 32)
+DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 32)
+DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 32)
+#else
+DEFINE_MM_REG_WRITE(baudr, DW_SPI_REG_BAUDR, 16)
 DEFINE_MM_REG_WRITE(imr, DW_SPI_REG_IMR, 8)
 DEFINE_MM_REG_READ(imr, DW_SPI_REG_IMR, 8)
 DEFINE_MM_REG_READ(isr, DW_SPI_REG_ISR, 8)
+#endif
 
 DEFINE_SET_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)
 DEFINE_CLEAR_BIT_OP(ssienr, DW_SPI_REG_SSIENR, DW_SPI_SSIENR_SSIEN_BIT)

drivers/spi/spi_dw_regs.h

@@ -43,9 +43,6 @@ extern "C" {
 /* Register helpers */
 DEFINE_MM_REG_WRITE(ctrlr0, DW_SPI_REG_CTRLR0, 32)
 DEFINE_MM_REG_READ(ctrlr0, DW_SPI_REG_CTRLR0, 32)
-DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 16)
-DEFINE_MM_REG_READ(ctrlr1, DW_SPI_REG_CTRLR1, 16)
-DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 8)
 DEFINE_MM_REG_WRITE(txftlr, DW_SPI_REG_TXFTLR, 32)
 DEFINE_MM_REG_WRITE(rxftlr, DW_SPI_REG_RXFTLR, 32)
 DEFINE_MM_REG_READ(rxftlr, DW_SPI_REG_RXFTLR, 32)
@@ -54,6 +51,16 @@ DEFINE_MM_REG_WRITE(dr, DW_SPI_REG_DR, 32)
 DEFINE_MM_REG_READ(dr, DW_SPI_REG_DR, 32)
 DEFINE_MM_REG_READ(ssi_comp_version, DW_SPI_REG_SSI_COMP_VERSION, 32)
 
+#ifdef CONFIG_SPI_DW_ACCESS_WORD_ONLY
+DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 32)
+DEFINE_MM_REG_READ(ctrlr1, DW_SPI_REG_CTRLR1, 32)
+DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 32)
+#else
+DEFINE_MM_REG_WRITE(ctrlr1, DW_SPI_REG_CTRLR1, 16)
+DEFINE_MM_REG_READ(ctrlr1, DW_SPI_REG_CTRLR1, 16)
+DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 8)
+#endif
+
 /* ICR is on a unique bit */
 DEFINE_TEST_BIT_OP(icr, DW_SPI_REG_ICR, DW_SPI_SR_ICR_BIT)
 #define clear_interrupts(addr) test_bit_icr(addr)

dts/arc/arc_hsdk.dtsi

@@ -108,7 +108,7 @@
 		gpio0: gpio@f0003000 {
 			compatible = "snps,designware-gpio";
 			reg = <0xf0003000 0x1000>;
-			bits = <32>;
+			bits = <24>;
 			label = "GPIO_0";
 			interrupt-parent = <&idu_intc>;
 
@@ -181,7 +181,7 @@
 			#size-cells = <0>;
 			reg = <0xf0022000 0x1000>;
 			interrupts = <42 1>;
-			label = "SPI_1";
+			label = "SPI_2";
 			status = "disabled";
 		};
 

samples/gui/lvgl/boards/hsdk.conf

@@ -0,0 +1,4 @@
+CONFIG_ILI9340=y
+CONFIG_ILI9340_LCD_SEEED_TFTV2=y
+
+CONFIG_LVGL=y

soc/arc/snps_arc_hsdk/dts_fixup.h

@@ -16,4 +16,54 @@
 #define DT_UART_NS16550_PORT_0_NAME	 DT_NS16550_F0005000_LABEL
 #define DT_UART_NS16550_PORT_0_IRQ_PRI	 DT_NS16550_F0005000_IRQ_0_PRIORITY
 
+/*
+ * GPIO configuration
+ */
+#define DT_GPIO_DW_0_BASE_ADDR	DT_SNPS_DESIGNWARE_GPIO_F0003000_BASE_ADDRESS
+#define DT_GPIO_DW_0_BITS		DT_SNPS_DESIGNWARE_GPIO_F0003000_BITS
+#define CONFIG_GPIO_DW_0_NAME	DT_SNPS_DESIGNWARE_GPIO_F0003000_LABEL
+#define DT_GPIO_DW_0_IRQ		DT_SNPS_DESIGNWARE_GPIO_F0003000_IRQ_0
+#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0003000_IRQ_0_PRIORITY
+#define DT_GPIO_DW_0_IRQ_FLAGS	0
+
+/*
+ * SPI configuration
+ */
+
+#define DT_SPI_0_BASE_ADDRESS	DT_SNPS_DESIGNWARE_SPI_F0020000_BASE_ADDRESS
+#define DT_SPI_0_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_F0020000_CLOCK_FREQUENCY
+#define DT_SPI_0_NAME		DT_SNPS_DESIGNWARE_SPI_F0020000_LABEL
+#define DT_SPI_0_IRQ		DT_SNPS_DESIGNWARE_SPI_F0020000_IRQ_0
+#define DT_SPI_0_IRQ_PRI		DT_SNPS_DESIGNWARE_SPI_F0020000_IRQ_0_PRIORITY
+
+#define DT_SPI_1_BASE_ADDRESS	DT_SNPS_DESIGNWARE_SPI_F0021000_BASE_ADDRESS
+#define DT_SPI_1_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_F0021000_CLOCK_FREQUENCY
+#define DT_SPI_1_NAME		DT_SNPS_DESIGNWARE_SPI_F0021000_LABEL
+#define DT_SPI_1_IRQ		DT_SNPS_DESIGNWARE_SPI_F0021000_IRQ_0
+#define DT_SPI_1_IRQ_PRI		DT_SNPS_DESIGNWARE_SPI_F0021000_IRQ_0_PRIORITY
+
+#define DT_SPI_2_BASE_ADDRESS	DT_SNPS_DESIGNWARE_SPI_F0022000_BASE_ADDRESS
+#define DT_SPI_2_CLOCK_FREQUENCY DT_SNPS_DESIGNWARE_SPI_F0022000_CLOCK_FREQUENCY
+#define DT_SPI_2_NAME		DT_SNPS_DESIGNWARE_SPI_F0022000_LABEL
+#define DT_SPI_2_IRQ		DT_SNPS_DESIGNWARE_SPI_F0022000_IRQ_0
+#define DT_SPI_2_IRQ_PRI		DT_SNPS_DESIGNWARE_SPI_F0022000_IRQ_0_PRIORITY
+
+#define DT_SPI_DW_IRQ_FLAGS	0
+
+/*
+ * seeed TFT TOUCH SHIELD configuration
+ */
+
+#define DT_INST_0_ILITEK_ILI9340_BUS_NAME		DT_SPI_2_NAME
+#define DT_INST_0_ILITEK_ILI9340_SPI_MAX_FREQUENCY		12000000
+#define DT_INST_0_ILITEK_ILI9340_BASE_ADDRESS		1
+
+#define DT_INST_0_ILITEK_ILI9340_CS_GPIOS_CONTROLLER	CONFIG_GPIO_DW_0_NAME
+#define	DT_INST_0_ILITEK_ILI9340_CS_GPIOS_PIN		9
+
+#define DT_INST_0_ILITEK_ILI9340_CMD_DATA_GPIOS_CONTROLLER	CONFIG_GPIO_DW_0_NAME
+#define	DT_INST_0_ILITEK_ILI9340_CMD_DATA_GPIOS_PIN		21
+
+#define DT_INST_0_ILITEK_ILI9340_LABEL	"DISPLAY"
+
 /* End of SoC Level DTS fixup file */