soc: xtensa: intel_adsp: restore bootctl with per-core state #68894
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When exiting PM_STATE_SOFT_OFF, the primary core state is always used to restore bootctl register and the clock and power gating settings. This can lead to problems if non-primary core is powered up and down many times before primary core 0 is powered down the first time. The saved state in core_desc[0].bctl will be null, and as a result- power gating and clock gating is not disabled correctly for non-primary cores. Link: thesofproject/sof#8642 Signed-off-by: Kai Vehmanen <[email protected]>
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| @@ -354,7 +354,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) | |||
| if (state == PM_STATE_SOFT_OFF) { | |||
| /* restore clock gating state */ | |||
| DSPCS.bootctl[cpu].bctl |= | |||
| (core_desc[0].bctl & DSPBR_BCTL_WAITIPCG); | |||
| (core_desc[cpu].bctl & DSPBR_BCTL_WAITIPCG); | |||
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this code dates back to 1631d2d
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When exiting PM_STATE_SOFT_OFF, the primary core state is always used to restore bootctl register and the clock and power gating settings.
This can lead to problems if non-primary core is powered up and down many times before primary core 0 is powered down the first time. The saved state in core_desc[0].bctl will be null, and as a result- power gating and clock gating is not disabled correctly for non-primary cores.
Link: thesofproject/sof#8642