Still more MediaTek updates

arch/xtensa/core/prep_c.c

@@ -13,6 +13,13 @@ extern FUNC_NORETURN void z_cstart(void);
 /* defined by the SoC in case of CONFIG_SOC_HAS_RUNTIME_NUM_CPUS=y */
 extern void soc_num_cpus_init(void);
 
+/* Make sure the platform configuration matches what the toolchain
+ * thinks the hardware is doing.
+ */
+#ifdef CONFIG_DCACHE_LINE_SIZE
+BUILD_ASSERT(CONFIG_DCACHE_LINE_SIZE == XCHAL_DCACHE_LINESIZE);
+#endif
+
 /**
  *
  * @brief Prepare to and run C code

boards/mediatek/mt8186/mt8186_adsp.dts

@@ -37,12 +37,12 @@
 			#interrupt-cells = <3>;
 		};
 
-		intc2: intc@10680010 {
+		intc2: intc@10680050 {
 			compatible = "mediatek,adsp_intc";
 			interrupt-controller;
 			#interrupt-cells = <3>;
-			reg = <0x10680010 4>;
-			status-reg = <0x10680050>;
+			reg = <0x10680050 4>;
+			status-reg = <0x10680010>;
 			interrupts = <2 0 0>;
 			mask = <0x3f>;
 			interrupt-parent = <&core_intc>;

boards/mediatek/mt8188/mt8188_adsp.dts

@@ -38,12 +38,12 @@
 			#interrupt-cells = <3>;
 		};
 
-		intc2: intc@10b80010 {
+		intc2: intc@10b80050 {
 			compatible = "mediatek,adsp_intc";
 			interrupt-controller;
 			#interrupt-cells = <3>;
-			reg = <0x10b80010 4>;
-			status-reg = <0x10b80050>;
+			reg = <0x10b80050 4>;
+			status-reg = <0x10b80010>;
 			interrupts = <2 0 0>;
 			mask = <0x3f>;
 			interrupt-parent = <&core_intc>;

boards/mediatek/mt8195/mt8195_adsp.dts

@@ -18,7 +18,13 @@
 	dram0: memory@60000000 {
 		device_type = "memory";
 		compatible = "mmio-sram";
-		reg = <0x60000000 DT_SIZE_M(17)>;
+		reg = <0x60000000 DT_SIZE_K(13824)>;
+	};
+
+	dram1: memory@60e80000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x60e80000 DT_SIZE_K(2560)>;
 	};
 
 	soc {

boards/mediatek/mt8196/mt8196_adsp.dts

@@ -21,10 +21,10 @@
 		reg = <0x90000000 DT_SIZE_M(6)>;
 	};
 
-	dram1: memory@90700000 {
+	dram1: memory@90800000 {
 		device_type = "memory";
 		compatible = "mmio-sram";
-		reg = <0x90700000 DT_SIZE_M(1)>;
+		reg = <0x90800000 DT_SIZE_M(1)>;
 	};
 
 	soc {
@@ -88,16 +88,16 @@
 			interrupts = <8 0 0>;
 		};
 
-		mbox0: mbox@1a360100 {
+		mbox0: mbox@1a350100 {
 			compatible = "mediatek,mbox";
-			reg = <0x1a360100 16>;
+			reg = <0x1a350100 16>;
 			interrupt-parent = <&intc_g2>;
 			interrupts = <6 0 0>;
 		};
 
-		mbox1: mbox@1a370100 {
+		mbox1: mbox@1a360100 {
 			compatible = "mediatek,mbox";
-			reg = <0x1a370100 16>;
+			reg = <0x1a360100 16>;
 			interrupt-parent = <&intc_g2>;
 			interrupts = <7 0 0>;
 		};

boards/qemu/xtensa/Kconfig.defconfig

@@ -9,4 +9,8 @@ config BUILD_OUTPUT_BIN
 config IPM_CONSOLE_STACK_SIZE
 	default 2048 if IPM_CONSOLE_RECEIVER
 
+# Must match XCHAL_DCACHE_LINESIZE form core-isa.h
+config DCACHE_LINE_SIZE
+	default 32
+
 endif # BOARD_QEMU_XTENSA

drivers/console/Kconfig

@@ -284,4 +284,20 @@ config WINSTREAM_CONSOLE
 
 	  See the WINSTREAM Kconfig help for more information.
 
+config WINSTREAM_CONSOLE_STATIC
+	bool "Use static/linkable memory for the winstream console"
+	default y if !SOC_FAMILY_INTEL_ADSP
+	help
+	  The winstream console can be configured to use simple linker
+	  memory which can help avoid manual memory management at the
+	  platform layer.  The memory should be pointed to by the
+	  symbol "_winstream_console_buf" and have size set by
+	  CONFIG_WINSTREAM_CONSOLE_SIZE.
+
+config WINSTREAM_CONSOLE_STATIC_SIZE
+	int "Size of winstream console buffer"
+	default 32768
+	help
+	  Size of winstream console buffer, in bytes
+
 endif # CONSOLE

drivers/console/winstream_console.c

@@ -12,8 +12,10 @@
 #include <zephyr/devicetree.h>
 #include <zephyr/cache.h>
 
+#ifdef SOC_FAMILY_INTEL_ADSP
 #include <adsp_memory.h>
 #include <mem_window.h>
+#endif
 
 struct k_spinlock trace_lock;
 
@@ -58,19 +60,70 @@ static void winstream_console_hook_install(void)
 #endif
 }
 
+/* This gets optionally defined by the platform layer as it needs (it
+ * might want to go in a special location to coordinate with linux
+ * userspace, etc...)
+ */
+extern char _winstream_console_buf[];
+
+/* This descriptor with a 96-bit magic number gets linked into the
+ * binary when enabled so that external tooling can easily find it at
+ * runtime (e.g. by searching the binary image file, etc...)
+ */
+#define WINSTREAM_CONSOLE_MAGIC1 0xd06a5f74U
+#define WINSTREAM_CONSOLE_MAGIC2 0x004fe279U
+#define WINSTREAM_CONSOLE_MAGIC3 0xf9bdb8cdU
+
+struct winstream_console_desc {
+	uint32_t magic1;
+	uint32_t magic2;
+	uint32_t magic3;
+	uint32_t buf_addr;
+	uint32_t size;
+};
+
+static const __used struct winstream_console_desc wsdesc = {
+	.magic1 = WINSTREAM_CONSOLE_MAGIC1,
+	.magic2 = WINSTREAM_CONSOLE_MAGIC2,
+	.magic3 = WINSTREAM_CONSOLE_MAGIC3,
+	.buf_addr = (uint32_t) &_winstream_console_buf,
+	.size = CONFIG_WINSTREAM_CONSOLE_STATIC_SIZE,
+};
 
 static int winstream_console_init(void)
 {
+	void *buf = NULL;
+	size_t size = 0;
+
+#ifdef SOC_FAMILY_INTEL_ADSP
+	/* These have a SOC-specific "mem_window" device.  FIXME: The
+	 * type handling is backwards here.  We shouldn't be grabbing
+	 * an arbitrary DTS alias and assuming it's a mem_window at
+	 * runtime, that's not safe.  The mem_window init code (which
+	 * is typesafe by construction) should be detecting that it's
+	 * supposed to be the console and starting the console hook
+	 * registration process.
+	 */
 	const struct device *dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
 
 	if (!device_is_ready(dev)) {
 		return -ENODEV;
 	}
 	const struct mem_win_config *config = dev->config;
-	void *buf =
-		sys_cache_uncached_ptr_get((__sparse_force void __sparse_cache *)config->mem_base);
+	buf = sys_cache_uncached_ptr_get((__sparse_force void __sparse_cache *)config->mem_base);
+	size = config->size;
+#endif
+
+#ifdef CONFIG_WINSTREAM_CONSOLE_STATIC
+	/* Dirty trick to prevent linker garbage collection */
+	_winstream_console_buf[0] = ((volatile char*) &wsdesc)[0];
+
+	buf = &_winstream_console_buf;
+	size = CONFIG_WINSTREAM_CONSOLE_STATIC_SIZE;
+#endif
 
-	winstream = sys_winstream_init(buf, config->size);
+	__ASSERT_NO_MSG(buf != NULL && size != 0);
+	winstream = sys_winstream_init(buf, size);
 	winstream_console_hook_install();
 
 	return 0;

soc/mediatek/mt8xxx/Kconfig.defconfig

@@ -31,11 +31,32 @@ config IRQ_OFFLOAD_NESTED
 	default n if SOC_SERIES_MT818X
 	default y
 
+config CPU_HAS_DCACHE
+	default y
+config DCACHE
+	default y
+config CACHE_MANAGEMENT
+	default y
+config DCACHE_LINE_SIZE
+	default 128
+
+config NOCACHE_MEMORY
+	default y
+
 config MTK_ADSP_TIMER
 	default y
 config XTENSA_TIMER
 	default n
 
+config CONSOLE
+	default y
+config WINSTREAM_CONSOLE
+	default y
+config WINSTREAM
+	default y
+config LOG_BACKEND_ADSP
+	default y if LOG
+
 config XTENSA_CCOUNT_HZ
 	default 720000000 if SOC_MT8195
 	default 400000000 if SOC_MT8186

soc/mediatek/mt8xxx/linker.ld

@@ -65,6 +65,15 @@ SECTIONS {
     *(.gnu.linkonce.h.*)
   } > dram
 
+  /* SOF extended manifest */
+  . = ALIGN(16);
+  _fw_metadata_start = .;
+  .fw_metadata : {
+    KEEP (*(.fw_metadata))
+    . = ALIGN(16);
+  } > dram
+  _fw_metadata_end = .;
+
 #include <zephyr/linker/common-rom.ld>
 #include <snippets-rom-sections.ld>
 
@@ -101,6 +110,11 @@ SECTIONS {
   _end = .;
   _mtk_adsp_dram_end = .;
 
+  .nocache (NOLOAD) : {
+    . = ALIGN(4096);
+    *(.nocache .nocache.*)
+  } > dram
+
   /* Non-runtime-loaded sections below */
 
 #include <zephyr/linker/debug-sections.ld>

soc/mediatek/mt8xxx/mbox.c

@@ -57,7 +57,6 @@ struct mtk_mbox {
 
 struct mbox_cfg {
 	volatile struct mtk_mbox *mbox;
-	uint32_t irq;
 };
 
 struct mbox_data {
@@ -85,7 +84,12 @@ void mtk_adsp_mbox_signal(const struct device *mbox, uint32_t chan)
 	}
 }
 
-static void mbox_isr(const void *arg)
+#define DEF_DEVPTR(N) DEVICE_DT_INST_GET(N),
+const struct device * const mbox_devs[] = {
+	DT_INST_FOREACH_STATUS_OKAY(DEF_DEVPTR)
+};
+
+static void mbox_handle(const void *arg)
 {
 	const struct mbox_cfg *cfg = ((struct device *)arg)->config;
 	struct mbox_data *data = ((struct device *)arg)->data;
@@ -101,11 +105,17 @@ static void mbox_isr(const void *arg)
 	cfg->mbox->in_cmd_clr = cfg->mbox->in_cmd; /* ACK */
 }
 
+static void mbox_isr(const void *arg)
+{
+	for (int i = 0; i < ARRAY_SIZE(mbox_devs); i++) {
+		mbox_handle(mbox_devs[i]);
+	}
+}
+
 #define DEF_IRQ(N)							\
 	{ IRQ_CONNECT(DT_INST_IRQN(N), 0, mbox_isr, DEVICE_DT_INST_GET(N), 0); \
 	  irq_enable(DT_INST_IRQN(N)); }
 
-
 static int mbox_init(void)
 {
 	DT_INST_FOREACH_STATUS_OKAY(DEF_IRQ);
@@ -117,7 +127,7 @@ SYS_INIT(mbox_init, POST_KERNEL, 0);
 #define DEF_DEV(N)							\
 	static struct mbox_data dev_data##N;				\
 	static const struct mbox_cfg dev_cfg##N =			\
-		{ .irq  = DT_INST_IRQN(N), .mbox = (void *)DT_INST_REG_ADDR(N), }; \
+		{ .mbox = (void *)DT_INST_REG_ADDR(N), };		\
 	DEVICE_DT_INST_DEFINE(N, NULL, NULL, &dev_data##N, &dev_cfg##N,	\
 			      POST_KERNEL, 0, NULL);