Merge pull request #140 from zeroasiccorp/fix-lint

fix lint
zeroasiccorp · Dec 17, 2024 · 741985e · 741985e
2 parents 242a98b + 0d9909d
commit 741985e
Show file tree

Hide file tree

Showing 3 changed files with 8 additions and 8 deletions.
diff --git a/.flake8 b/.flake8
@@ -1,5 +1,5 @@
 [flake8]
-extend-exclude = testbench/build
+extend-exclude = testbench/build,build,.venv
 max-line-length = 100
 ignore =
     E125,

diff --git a/examples/adder/pin_constraints.py b/examples/adder/pin_constraints.py
@@ -42,13 +42,13 @@ def generate_mapped_constraints(part_name):
         for i in range(8):
             pin_constraints[f'b[{i}]'] = {
                 "direction": "input",
-                "pin": f'gpio_in[{i+8}]'
+                "pin": f'gpio_in[{i + 8}]'
             }
 
         for i in range(9):
             pin_constraints[f'y[{i}]'] = {
                 "direction": "output",
-                "pin": f'gpio_out[{i+16}]'
+                "pin": f'gpio_out[{i + 16}]'
             }
 
     else:
@@ -82,7 +82,7 @@ def generate_raw_constraints():
         else:
             pin_constraints[f'y[{i}]'] = {
                 "direction": "output",
-                "pin": f'pad_out_1_5[{i-8}]'
+                "pin": f'pad_out_1_5[{i - 8}]'
             }
 
     return pin_constraints

diff --git a/logik/templates/logik_demo/umi_pin_constraints.py b/logik/templates/logik_demo/umi_pin_constraints.py
@@ -67,7 +67,7 @@ def generate_umi_pin_constraints(fpga_ports_per_umi=300,
             umi_bus_index += 1
 
             for j in range(umi_cmd_width):
-                cur_signal = f'{port}_cmd[{i*umi_cmd_width+j}]'
+                cur_signal = f'{port}_cmd[{i * umi_cmd_width + j}]'
                 mapped_signal_name = f"umi_io_{cur_dir_short}[{umi_bus_index}]"
                 umi_to_fpga_pin_map[cur_signal] = {
                     "direction": cur_dir,
@@ -76,7 +76,7 @@ def generate_umi_pin_constraints(fpga_ports_per_umi=300,
                 umi_bus_index += 1
 
             for j in range(umi_addr_width):
-                cur_signal = f'{port}_dstaddr[{i*umi_addr_width+j}]'
+                cur_signal = f'{port}_dstaddr[{i * umi_addr_width + j}]'
                 mapped_signal_name = f"umi_io_{cur_dir_short}[{umi_bus_index}]"
                 umi_to_fpga_pin_map[cur_signal] = {
                     "direction": cur_dir,
@@ -85,7 +85,7 @@ def generate_umi_pin_constraints(fpga_ports_per_umi=300,
                 umi_bus_index += 1
 
             for j in range(umi_addr_width):
-                cur_signal = f'{port}_srcaddr[{i*umi_addr_width+j}]'
+                cur_signal = f'{port}_srcaddr[{i * umi_addr_width + j}]'
                 mapped_signal_name = f"umi_io_{cur_dir_short}[{umi_bus_index}]"
                 umi_to_fpga_pin_map[cur_signal] = {
                     "direction": cur_dir,
@@ -94,7 +94,7 @@ def generate_umi_pin_constraints(fpga_ports_per_umi=300,
                 umi_bus_index += 1
 
             for j in range(umi_data_width):
-                cur_signal = f'{port}_data[{i*umi_data_width+j}]'
+                cur_signal = f'{port}_data[{i * umi_data_width + j}]'
                 mapped_signal_name = f"umi_io_{cur_dir_short}[{umi_bus_index}]"
                 umi_to_fpga_pin_map[cur_signal] = {
                     "direction": cur_dir,