switch download url

logik/fpgas/_common.py

@@ -1,19 +1,16 @@
 # Copyright 2024 Zero ASIC Corporation
 # Licensed under the MIT License (see LICENSE for details)
 
-from siliconcompiler.package import register_private_github_data_source
+fpga_version = 'v0.1.22'
 
 
-fpga_version = 'v0.1.22'
+def get_package_name(part_name):
+    return f"logik-fpga-{part_name}"
 
 
-def register_package(fpga, package_name, artifact):
-    register_private_github_data_source(
-        fpga,
-        package_name,
-        repository='zeroasiccorp/logik',
-        release=fpga_version,
-        artifact=artifact)
+def get_download_url(part_name):
+    root = "https://github.com/zeroasiccorp/logik/releases/download"
+    return f"{root}/{fpga_version}/{part_name}_cad.tar.gz"
 
 
 def set_fpga_resources(fpga):

logik/fpgas/logik_demo.py

@@ -37,12 +37,11 @@ def setup(chip):
 
     # Settings common to all parts in family
     for part_name in all_part_names:
-
-        fpga = FPGA(chip, part_name, package=f'logik-{part_name}')
-        _common.register_package(
-            fpga,
-            f'logik-{part_name}',
-            f'{part_name}_cad.tar.gz')
+        fpga = FPGA(chip, part_name, package=_common.get_package_name(part_name))
+        fpga.register_package_source(
+            _common.get_package_name(part_name),
+            path=_common.get_download_url(part_name),
+            ref=_common.fpga_version)
 
         fpga.set('fpga', part_name, 'vendor', vendor)