Merge #19170 #19185 #19187

19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht

### Contribution description

This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`.

**[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards.

This PR depends on PR #19166 and includes this PR for the moment.

### Testing procedure

t.b.d.

### Issues/PRs references

Depends on PR #19166

19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht

### Contribution description

This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103.

### Testing procedure

Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing.
```
BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash  (until PR #19170 is merged only `seeedstudio
```
With the GPIO PB8 and PB9 connected, the following test sequence should work:
```
> init_out 1 8
> init_int 1 9 2 0
GPIO_PIN(1, 9) successfully initialized as ext int
> set 1 8
INT: external interrupt from pin 9
> clear 1 8
INT: external interrupt from pin 9
```


### Issues/PRs references


19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht

### Contribution description

This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103.

Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs.

### Testing procedure

The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing.
```
BOARD=seeedstudio-gd32 make -C tests/periph_pm flash
```
The test output should be:
```
main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test)
...
mode 0 blockers: 1 
mode 1 blockers: 2 
mode 2 blockers: 0 
Lowest allowed mode: 2
```
Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds
```
> set_rtc 1 5
Setting power mode 1 for 5 seconds.
␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> 
```
while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart.
```
> set_rtc 0 5
Setting power mode 0 for 5 seconds.
main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test)
...
mode 0 blockers: 1 
mode 1 blockers: 2 
mode 2 blockers: 0 
Lowest allowed mode: 2
> 
```
The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards.

### Issues/PRs references

Co-authored-by: Gunar Schorcht <[email protected]>

boards/common/gd32v/Kconfig

@@ -0,0 +1,20 @@
+# Copyright (c) 2023 Gunar Schorcht
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config BOARD_HAS_HXTAL
+    bool
+    help
+        Indicates that the board is providing an HXTAL oscillator
+
+config BOARD_HAS_LXTAL
+    bool
+    help
+        Indicates that the board is providing an LXTAL oscillator
+
+config CLOCK_HXTAL
+    int
+    default 8000000

boards/common/gd32v/Makefile.features

@@ -0,0 +1 @@
+CPU = gd32v

boards/common/gd32v/Makefile.include

@@ -0,0 +1,14 @@
+# include this module into the build
+INCLUDES += -I$(RIOTBOARD)/common/gd32v/include
+
+# configure the serial interface
+PORT_LINUX ?= /dev/ttyUSB0
+PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
+
+# configure the flasher
+PROGRAMMER ?= openocd
+OPENOCD_CONFIG ?= $(RIOTBOARD)/common/gd32v/dist/openocd.cfg
+OPENOCD_DEBUG_ADAPTER ?= ftdi
+OPENOCD_FTDI_ADAPTER ?= openocd-usb
+OPENOCD_TRANSPORT = jtag
+OPENOCD_RESET_USE_CONNECT_ASSERT_SRST = 1

boards/common/gd32v/doc.txt

@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2023 Gunar Schorcht
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @defgroup    boards_common_gd32v GD32V Common Configuration
+ * @ingroup     boards_common
+ * @brief       Definitions and configurations that are common for
+ *              all GD32VF103 boards.
+ *
+ * All boards using a MCU from the GD32VF103 family share some parts of their
+ * configuration.
+ */

boards/common/gd32v/include/cfg_timer_default.h

@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) 2020 Koen Zandberg <[email protected]>
+ *               2023 Gunar Schorcht <[email protected]>
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_common_gd32v
+ * @{
+ *
+ * @file
+ * @brief       Default timer configuration for GD32VF103 boards
+ *
+ * @author      Koen Zandberg <[email protected]>
+ * @author      Gunar Schorcht <[email protected]>
+ */
+
+#ifndef CFG_TIMER_DEFAULT_H
+#define CFG_TIMER_DEFAULT_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name   Timer configuration
+ *
+ * All GD32VF103xx variants have at least one advanced timer TIMER0 and two
+ * general timers TIMER1 and TIMER2. GD32VF10x8 and GD32VF10xB have two
+ * additional general timers TIMER3 and TIMER4.
+ *
+ * @{
+ */
+static const timer_conf_t timer_config[] = {
+    {
+        .dev      = TIMER1,
+        .max      = 0x0000ffff,
+        .rcu_mask = RCU_APB1EN_TIMER1EN_Msk,
+        .bus      = APB1,
+        .irqn     = TIMER1_IRQn
+    },
+    {
+        .dev      = TIMER2,
+        .max      = 0x0000ffff,
+        .rcu_mask = RCU_APB1EN_TIMER2EN_Msk,
+        .bus      = APB1,
+        .irqn     = TIMER2_IRQn
+    },
+#if defined(CPU_MODEL_GD32VF103C8T6) || defined(CPU_MODEL_GD32VF103CBT6) || \
+    defined(CPU_MODEL_GD32VF103R8T6) || defined(CPU_MODEL_GD32VF103RBT6) || \
+    defined(CPU_MODEL_GD32VF103T8U6) || defined(CPU_MODEL_GD32VF103TBU6) || \
+    defined(CPU_MODEL_GD32VF103V8T6) || defined(CPU_MODEL_GD32VF103VBT6)
+    {
+        .dev      = TIMER3,
+        .max      = 0x0000ffff,
+        .rcu_mask = RCU_APB1EN_TIMER3EN_Msk,
+        .bus      = APB1,
+        .irqn     = TIMER3_IRQn
+    },
+    {
+        .dev      = TIMER4,
+        .max      = 0x0000ffff,
+        .rcu_mask = RCU_APB1EN_TIMER4EN_Msk,
+        .bus      = APB1,
+        .irqn     = TIMER4_IRQn
+    }
+#endif
+};
+
+#define TIMER_0_IRQN        TIMER1_IRQn
+#define TIMER_1_IRQN        TIMER2_IRQn
+#define TIMER_2_IRQN        TIMER3_IRQn
+#define TIMER_3_IRQN        TIMER4_IRQn
+
+#define TIMER_NUMOF         ARRAY_SIZE(timer_config)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CFG_TIMER_DEFAULT_H */
+/** @} */

boards/common/gd32v/include/cfg_uart_default.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (C) 2020 Koen Zandberg <[email protected]>
+ *               2023 Gunar Schorcht <[email protected]>
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_common_gd32v
+ * @{
+ *
+ * @file
+ * @brief       Default UART configuration for GD32VF103 boards
+ *
+ * @author      Koen Zandberg <[email protected]>
+ * @author      Gunar Schorcht <[email protected]>
+ */
+
+#ifndef CFG_UART_DEFAULT_H
+#define CFG_UART_DEFAULT_H
+
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name   UART configuration
+ * @{
+ */
+static const uart_conf_t uart_config[] = {
+    {
+        .dev        = USART0,
+        .rcu_mask   = RCU_APB2EN_USART0EN_Msk,
+        .rx_pin     = GPIO_PIN(PORT_A, 10),
+        .tx_pin     = GPIO_PIN(PORT_A, 9),
+        .bus        = APB2,
+        .irqn       = USART0_IRQn,
+    },
+};
+
+#define UART_0_IRQN         USART0_IRQn
+
+#define UART_NUMOF          ARRAY_SIZE(uart_config)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CFG_UART_DEFAULT_H */
+/** @} */

boards/common/gd32v/include/periph_common_conf.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2020 Koen Zandberg <[email protected]>
+ *               2023 Gunar Schorcht <[email protected]>
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     boards_common_gd32v
+ * @{
+ *
+ * @file
+ * @brief       Common peripheral configuration for GD32VF103 boards
+ *
+ * @author      Koen Zandberg <[email protected]>
+ * @author      Gunar Schorcht <[email protected]>
+ */
+
+#ifndef PERIPH_COMMON_CONF_H
+#define PERIPH_COMMON_CONF_H
+
+#include "macros/units.h"
+#include "periph_cpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CLOCK_CORECLOCK         MHZ(108)    /**< CPU clock frequency in Hz */
+
+#define CLOCK_AHB               CLOCK_CORECLOCK /**< Equal to the CPU clock */
+#define CLOCK_APB1              CLOCK_AHB/2     /**< Half AHB clock */
+#define CLOCK_APB2              CLOCK_AHB       /**< Equal to the AHB clock */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PERIPH_COMMON_CONF_H */
+/** @} */

boards/seeedstudio-gd32/Kconfig

@@ -12,21 +12,10 @@ config BOARD_SEEEDSTUDIO_GD32
     bool
     default y
     select CPU_MODEL_GD32VF103VBT6
-    select HAS_PERIPH_UART
     select BOARD_HAS_HXTAL
     select BOARD_HAS_LXTAL
+    select HAS_PERIPH_TIMER
+    select HAS_PERIPH_UART
     select HAVE_SAUL_GPIO
 
-config BOARD_HAS_HXTAL
-    bool
-    help
-        Indicates that the board is providing an HXTAL oscillator
-
-config BOARD_HAS_LXTAL
-    bool
-    help
-        Indicates that the board is providing an LXTAL oscillator
-
-config CLOCK_HXTAL
-    int
-    default 8000000
+source "$(RIOTBOARD)/common/gd32v/Kconfig"

boards/seeedstudio-gd32/Makefile.dep

@@ -1,3 +1,5 @@
 ifneq (,$(filter saul_default,$(USEMODULE)))
   USEMODULE += saul_gpio
 endif
+
+include $(RIOTBOARD)/common/gd32v/Makefile.dep

boards/seeedstudio-gd32/Makefile.features

@@ -1,6 +1,7 @@
-CPU = gd32v
 CPU_MODEL = gd32vf103vbt6
 
 # Put defined MCU peripherals here (in alphabetical order)
 FEATURES_PROVIDED += periph_timer
 FEATURES_PROVIDED += periph_uart
+
+include $(RIOTBOARD)/common/gd32v/Makefile.features

boards/seeedstudio-gd32/Makefile.include

@@ -1,10 +1 @@
-# configure the serial interface
-PORT_LINUX ?= /dev/ttyUSB0
-PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))
-
-# configure the flasher
-PROGRAMMER ?= openocd
-OPENOCD_DEBUG_ADAPTER ?= ftdi
-OPENOCD_FTDI_ADAPTER ?= openocd-usb
-OPENOCD_TRANSPORT = jtag
-OPENOCD_RESET_USE_CONNECT_ASSERT_SRST = 1
+include $(RIOTBOARD)/common/gd32v/Makefile.include

boards/seeedstudio-gd32/include/board.h

@@ -25,8 +25,6 @@
 extern "C" {
 #endif
 
-#include "macros/units.h"
-
 /**
  * @name    Button pin definitions
  * @{
@@ -67,14 +65,6 @@ extern "C" {
 #define LED_BLUE_PIN        LED2_PIN    /**< LED2 is blue */
 /** @} */
 
-/**
- * @name    Xtimer configuration
- * @{
- */
-#define XTIMER_HZ                   MHZ(1)
-#define XTIMER_WIDTH                (16)
-/** @} */
-
 #ifdef __cplusplus
 }
 #endif

boards/seeedstudio-gd32/include/periph_conf.h

@@ -19,15 +19,14 @@
 #ifndef PERIPH_CONF_H
 #define PERIPH_CONF_H
 
-#include "macros/units.h"
 #include "periph_cpu.h"
+#include "periph_common_conf.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif
+#include "cfg_timer_default.h"
+#include "cfg_uart_default.h"
 
 #ifndef CONFIG_BOARD_HAS_HXTAL
-#define CONFIG_BOARD_HAS_HXTAL  1   /**< This board provides an high frequency oscillator */
+#define CONFIG_BOARD_HAS_HXTAL  1   /**< The board provides a high frequency oscillator. */
 #endif
 
 #ifndef CONFIG_BOARD_HAS_LXTAL
@@ -38,54 +37,9 @@ extern "C" {
 #define CONFIG_CLOCK_HXTAL      MHZ(8)      /**< HXTAL frequency */
 #endif
 
-#define CLOCK_CORECLOCK         MHZ(108)    /**< CPU clock frequency in Hz */
-
-/**
- * @name   Timer configuration
- * @{
- */
-static const timer_conf_t timer_config[] = {
-    {
-        .dev      = TIMER2,
-        .max      = 0x0000ffff,
-        .rcu_mask = RCU_APB1EN_TIMER2EN_Msk,
-        .bus      = APB1,
-        .irqn     = TIMER2_IRQn
-    },
-    {
-        .dev      = TIMER3,
-        .max      = 0x0000ffff,
-        .rcu_mask = RCU_APB1EN_TIMER3EN_Msk,
-        .bus      = APB1,
-        .irqn     = TIMER3_IRQn
-    }
-};
-
-#define TIMER_0_IRQN        TIMER2_IRQn
-#define TIMER_1_IRQN        TIMER3_IRQn
-
-#define TIMER_NUMOF         ARRAY_SIZE(timer_config)
-/** @} */
-
-/**
- * @name   UART configuration
- * @{
- */
-static const uart_conf_t uart_config[] = {
-    {
-        .dev        = USART0,
-        .rcu_mask   = RCU_APB2EN_USART0EN_Msk,
-        .rx_pin     = GPIO_PIN(PORT_A, 10),
-        .tx_pin     = GPIO_PIN(PORT_A, 9),
-        .bus        = APB2,
-        .irqn       = USART0_IRQn,
-    },
-};
-
-#define UART_0_IRQN         USART0_IRQn
-
-#define UART_NUMOF          ARRAY_SIZE(uart_config)
-/** @} */
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #ifdef __cplusplus
 }