cpu/gd32v: add periph_gpio_irq support #19185

gschorcht · 2023-01-22T15:00:31Z

Contribution description

This PR provides the periph_gpio_irq support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103.

Testing procedure

Use a GD32VF103 board and flash tests/periph_gpio. Note: The Sipeed Longan Nano works also with seeedstudio-gd32 board defintion and could be used for testing.

BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash  (until PR #19170 is merged only `seeedstudio

With the GPIO PB8 and PB9 connected, the following test sequence should work:

> init_out 1 8
> init_int 1 9 2 0
GPIO_PIN(1, 9) successfully initialized as ext int
> set 1 8
INT: external interrupt from pin 9
> clear 1 8
INT: external interrupt from pin 9

Issues/PRs references

riot-ci · 2023-01-22T16:22:33Z

Murdock results

✔️ PASSED

ced6344 cpu/gd32v: add periph_gpio_irq support

Success	Failures	Total	Runtime
6796	0	6796	09m:47s

Artifacts

Documentation preview

benpicco · 2023-01-23T00:56:53Z

cpu/gd32v/periph/gpio.c

+    unsigned irqn = (pin_num < 5) ? EXTI0_IRQn + pin_num
+                                  : ((pin_num < 10) ? EXTI5_9_IRQn
+                                                    : EXTI10_15_IRQn);


That looks artsy, but makes it harder to understand what's going on.
Let's keep it simple 😉

static inline unsigned _irq_num(unsigned pin_num) { if (pin_num < 5) { return EXTI0_IRQn + pin_num; } if (pin_num < 10) { return EXTI5_9_IRQn; } return EXTI10_15_IRQn; }

benpicco · 2023-01-23T00:58:14Z

cpu/gd32v/periph/gpio.c

+     * the EXTI line with PB<n>, PC<n>, PD<n> and PE<n>. */
+    if (exti_ctx[pin_num].cb != 0) {
+        LOG_ERROR("EXTI line for GPIO_PIN(%u, %u) is already used.\n",
+                  port_num, pin_num);


I guess we can't detect which one it was inside the ISR?

Better add an assert(0) here as config errors should be caught early.

Initially I had an assert here, but since all other implementations don't check it, I replaced it with an error message.

We could detect which one already occupies the EXTI line by holding a gpio_t exti_used_by[16] array which would result into 48 extra bytes. I'm not sure whether this would be worth. We could use a compress port/pin num format so that 1 byte per EXTI line would be sufficient since the GD32VF103 has 5 ports at maximum and 16 pins each port.

Ah just for the debug output it's not needed.
I thought maybe there is a way to multiplex the interrupt itself, but probably not.

Unfortunatly not.

benpicco · 2023-01-23T17:29:17Z

Now needs a rebase, just squash directly.

Not sure if we really need the nice/expensive debug output if the limitation (only one interrupt / pin index, across all ports) is clearly documented.

gschorcht · 2023-01-23T17:35:42Z

Not sure if we really need the nice/expensive debug output if the limitation (only one interrupt / pin index, across all ports) is clearly documented

Should I remove it completely? I costs now 16 byte of RAM if NDEBUG is not defined and of course some ROM.

benpicco · 2023-01-23T17:53:34Z

I don't know how common of an error case that is, but indeed 16 bytes is not that much.
I'm fine with either really.

gschorcht · 2023-01-23T18:12:43Z

but indeed 16 bytes is not that much.

I wonder if this exti_line_port could even help and might be useful to avoid the following assertion error when a GPIO is reinitialized and the EXTI line is used by already used by that GPIO port, e.g. because the mode of the GPIO is changed during runtime.

By the way, all other implementations like STM32 allow to silently overwrite the port connected to an EXTI line, maybe exactly for that reason.

benpicco · 2023-01-23T18:36:39Z

Yea that makes sense, re-configuring the same pin should not fail.

gschorcht · 2023-01-23T19:03:28Z

Yea that makes sense, re-configuring the same pin should not fail.

The question is whether we allow the port associated with an EXTI line to be silently changed, as other implementations do, or whether we insist that the port not be changed. Could there be an intentional use case where the GPIOs port using an EXTI line changes during runtime, i.e. first a GPIO of one port uses the EXTI line and later a GPIO of another port 🤔

benpicco · 2023-01-23T19:28:36Z

Could there be an intentional use case where the GPIOs port using an EXTI line changes during runtime, i.e. first a GPIO of one port uses the EXTI line and later a GPIO of another port

Probably not, but I can imagine a use case where the callback function of a pin is changed at run-time by calling gpio_init_int() again.

gschorcht · 2023-01-23T19:58:52Z

Probably not, but I can imagine a use case where the callback function of a pin is changed at run-time by calling gpio_init_int() again.

Ok, but in that case the GPIO would be the same. Otherwise, we could give a hint of a configuration problem by an assertion failure.

gschorcht · 2023-01-23T20:10:24Z

Maybe fde09cc is the best solution. It helps to detect configuration errors during development but doesn't cost RAM and ROM when NDEBUG is defined.

benpicco

Please squash

benpicco · 2023-01-23T22:07:37Z

bors merge

19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

bors · 2023-01-23T22:12:14Z

Build failed (retrying...):

Murdock

19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

benpicco · 2023-01-23T22:31:53Z

bors merge

bors · 2023-01-23T22:31:55Z

Already running a review

bors · 2023-01-23T22:34:57Z

This PR was included in a batch that was canceled, it will be automatically retried

benpicco · 2023-01-23T22:35:32Z

bors cancel

bors merge

bors · 2023-01-23T22:35:34Z

Canceled.

19170: boards/sipeed-longan-nano: add definition for the Sipeed Longan Nano GD32VF103 board r=benpicco a=gschorcht ### Contribution description This PR add the support for the [Sipeed Longan Nano](https://longan.sipeed.com/en) board, a GD32VF103 development board with the GigaDevice GD32VF103CBT8 RISC-V MCU. This includes moving the common board definitions for GDV32F103 boards from `boards/seeedstudio-gd32` to `boards/common/gd32v`. **[Update]** At first glance, the existing peripheral definition for `seeedstudio-gd32` seems to fit exactly for `sipeed-longan-nano`. But at second glance it becomes clear that `seeedstudio-gd32` which is using the GD32VF103VBT6 instead of the GD32VF103CBT6 has more peripherals and much more peripheral pins are broken out. This allows a more extensive and flexible peripheral definition (more timers, more ADC pins, more UART interfaces, ...). So it doesn't seem to be a good idea to share the peripheral definitions between these boards. This PR depends on PR #19166 and includes this PR for the moment. ### Testing procedure t.b.d. ### Issues/PRs references Depends on PR #19166 19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

bors · 2023-01-23T22:41:29Z

Build failed (retrying...):

Murdock

19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=benpicco a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

bors · 2023-01-23T23:31:33Z

Build failed (retrying...):

Murdock

19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

bors · 2023-01-24T02:30:41Z

Build failed:

Murdock

kaspar030 · 2023-01-24T07:12:58Z

bors retry

19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

bors · 2023-01-24T09:05:06Z

Build failed:

Murdock

maribu · 2023-01-24T10:30:54Z

bors retry

The last CI failure (timeout while building) looks like a temporary issue with one of the workers.

19185: cpu/gd32v: add periph_gpio_irq support r=benpicco a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references Co-authored-by: Gunar Schorcht <[email protected]>

bors · 2023-01-24T12:08:37Z

Build failed:

Murdock

gschorcht · 2023-01-24T13:42:36Z

Build failed:

Murdock

unrelated error, restart bors

bors merge

bors · 2023-01-24T17:08:32Z

Build succeeded:

gschorcht requested review from leandrolanzieri, jia200x and MrKevinWeiss as code owners January 22, 2023 15:00

github-actions bot added Area: cpu Area: CPU/MCU ports Area: Kconfig Area: Kconfig integration labels Jan 22, 2023

gschorcht requested a review from bergzand January 22, 2023 15:03

benpicco reviewed Jan 23, 2023

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github-actions bot removed the Platform: RISC-V Platform: This PR/issue effects RISC-V-based platforms label Jan 23, 2023

benpicco approved these changes Jan 23, 2023

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gschorcht force-pushed the cpu/gd32v/periph_gpio_irq branch 2 times, most recently from ca5fb47 to a7690f6 Compare January 23, 2023 21:43

cpu/gd32v: add periph_gpio_irq support

ced6344

gschorcht force-pushed the cpu/gd32v/periph_gpio_irq branch from a7690f6 to ced6344 Compare January 23, 2023 21:51

bors bot merged commit f85366a into RIOT-OS:master Jan 24, 2023

gschorcht deleted the cpu/gd32v/periph_gpio_irq branch January 29, 2023 11:03

MrKevinWeiss added this to the Release 2023.04 milestone Apr 25, 2023

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cpu/gd32v: add periph_gpio_irq support #19185

cpu/gd32v: add periph_gpio_irq support #19185

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cpu/gd32v: add periph_gpio_irq support #19185

cpu/gd32v: add periph_gpio_irq support #19185

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