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Merge pull request #18260 from gschorcht/cpu/esp32/add_riscv_platform…
…_code cpu/esp32: add platform code for RISC-V based ESP32x SoCs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,14 @@ | ||
| # Copyright (c) 2022 Gunar Schorcht | ||
| # | ||
| # This file is subject to the terms and conditions of the GNU Lesser | ||
| # General Public License v2.1. See the file LICENSE in the top level | ||
| # directory for more details. | ||
| # | ||
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| config MODULE_ESP_RISCV | ||
| bool | ||
| depends on TEST_KCONFIG | ||
| depends on HAS_ARCH_ESP_RISCV | ||
| default y | ||
| help | ||
| Platform-dependent code for Xtensa-based ESP SoCs. |
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| MODULE=esp_riscv | ||
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| include $(RIOTBASE)/Makefile.base |
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| /* | ||
| * Copyright (C) 2022 Gunar Schorcht | ||
| * | ||
| * This file is subject to the terms and conditions of the GNU Lesser | ||
| * General Public License v2.1. See the file LICENSE in the top level | ||
| * directory for more details. | ||
| */ | ||
|
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| /** | ||
| * @ingroup cpu_esp_common | ||
| * @{ | ||
| * | ||
| * @file | ||
| * @brief Exception handling for RISC-V-based ESP SoCs | ||
| * | ||
| * @author Gunar Schorcht <[email protected]> | ||
| * @} | ||
| */ | ||
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| #include <inttypes.h> | ||
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| #include "kernel_defines.h" | ||
| #include "panic.h" | ||
| #include "periph/pm.h" | ||
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| #include "esp_attr.h" | ||
| #include "riscv/rvruntime-frames.h" | ||
| #include "rom/ets_sys.h" | ||
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| static const char *exceptions[] = { | ||
| "nil", | ||
| "0x1: PMP Instruction access fault", | ||
| "0x2: Illegal Instruction", | ||
| "0x3: Hardware Breakpoint/Watchpoint or EBREAK", | ||
| "nil", | ||
| "0x5: PMP Load access fault", | ||
| "nil", | ||
| "0x7: PMP Store access fault", | ||
| "0x8: ECALL from U mode", | ||
| "nil", | ||
| "nil", | ||
| "0xb: ECALL from M mode", | ||
| }; | ||
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| static RvExcFrame *_frame = NULL; | ||
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| void init_exceptions (void) | ||
| { | ||
| } | ||
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| void IRAM_ATTR xt_unhandled_exception(RvExcFrame *frame) | ||
| { | ||
| _frame = frame; | ||
| core_panic(PANIC_GENERAL_ERROR, "Unhandled exception"); | ||
| } | ||
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| void IRAM_ATTR panicHandler(RvExcFrame *frame) | ||
| { | ||
| _frame = frame; | ||
| core_panic(PANIC_GENERAL_ERROR, "Panic handler"); | ||
| } | ||
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| extern void heap_stats(void); | ||
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| void panic_arch(void) | ||
| { | ||
| if (_frame) { | ||
| /* TODO */ | ||
| ets_printf("Exception @0x%08"PRIx32", cause %s\n", | ||
| _frame->mepc, exceptions[_frame->mcause]); | ||
| } | ||
| #if defined(DEVELHELP) | ||
| heap_stats(); | ||
| #endif | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,97 @@ | ||
| /* | ||
| * Copyright (C) 2022 Gunar Schorcht | ||
| * | ||
| * This file is subject to the terms and conditions of the GNU Lesser | ||
| * General Public License v2.1. See the file LICENSE in the top level | ||
| * directory for more details. | ||
| */ | ||
|
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| /** | ||
| * @ingroup cpu_esp32 | ||
| * @{ | ||
| * | ||
| * @file | ||
| * @brief Implementation of the kernels irq interface | ||
| * | ||
| * @author Gunar Schorcht <[email protected]> | ||
| * | ||
| * @} | ||
| */ | ||
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| #include "irq_arch.h" | ||
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| #include "esp_attr.h" | ||
| #include "hal/interrupt_controller_types.h" | ||
| #include "hal/interrupt_controller_ll.h" | ||
| #include "soc/periph_defs.h" | ||
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| #define ENABLE_DEBUG 0 | ||
| #include "debug.h" | ||
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| #define RVHAL_EXCM_LEVEL 4 | ||
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| /** | ||
| * @brief Disable all maskable interrupts | ||
| */ | ||
| unsigned int IRAM_ATTR irq_disable(void) | ||
| { | ||
| uint32_t mstatus; | ||
| /* clear MIE bit in register mstatus */ | ||
| __asm__ volatile ("csrrc %0, mstatus, %1" : "=r"(mstatus) : "rK"(MSTATUS_MIE) : "memory"); | ||
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| /* save interrupt priority level threshold */ | ||
| uint32_t state = *((volatile uint32_t *)INTERRUPT_CORE0_CPU_INT_THRESH_REG); | ||
| /* set interrupt priority level threshold to exception level */ | ||
| *((volatile uint32_t *)INTERRUPT_CORE0_CPU_INT_THRESH_REG) = RVHAL_EXCM_LEVEL; | ||
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| /* set MIE bit in register mstatus */ | ||
| __asm__ volatile ("csrrs %0, mstatus, %1" : "=r"(mstatus) : "rK"(MSTATUS_MIE) : "memory"); | ||
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| DEBUG("%s %02x(%02x)\n", __func__, RVHAL_EXCM_LEVEL, (unsigned)state); | ||
| return state; | ||
| } | ||
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| /** | ||
| * @brief Enable all maskable interrupts | ||
| */ | ||
| unsigned int IRAM_ATTR irq_enable(void) | ||
| { | ||
| uint32_t state = *((volatile uint32_t *)INTERRUPT_CORE0_CPU_INT_THRESH_REG); | ||
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| /* set interrupt priority level threshold to 0 */ | ||
| *((volatile uint32_t *)INTERRUPT_CORE0_CPU_INT_THRESH_REG) = 0; | ||
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| /* small delay needed here */ | ||
| __asm__ volatile ( "nop" ); | ||
| __asm__ volatile ( "nop" ); | ||
| __asm__ volatile ( "nop" ); | ||
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| DEBUG("%s %02x(%02x)\n", __func__, 0, (unsigned)state); | ||
| return state; | ||
| } | ||
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| /** | ||
| * @brief Restore the state of the IRQ flags | ||
| */ | ||
| void IRAM_ATTR irq_restore(unsigned int state) | ||
| { | ||
| uint32_t old = *((volatile uint32_t *)INTERRUPT_CORE0_CPU_INT_THRESH_REG); | ||
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| /* set interrupt priority level threshold to old level */ | ||
| *((volatile uint32_t *)INTERRUPT_CORE0_CPU_INT_THRESH_REG) = state; | ||
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| /* small delay needed here */ | ||
| __asm__ volatile ( "nop" ); | ||
| __asm__ volatile ( "nop" ); | ||
| __asm__ volatile ( "nop" ); | ||
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| DEBUG("%s %02x(%02x)\n", __func__, (unsigned)state, (unsigned)old); | ||
| } | ||
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| /** | ||
| * @brief Test if IRQs are currently enabled | ||
| */ | ||
| bool IRAM_ATTR irq_is_enabled(void) | ||
| { | ||
| return *((volatile uint32_t *)INTERRUPT_CORE0_CPU_INT_THRESH_REG) == 0; | ||
| } |
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