cpu/esp32: add platform code for RISC-V based ESP32x SoCs

[gschorcht]

Contribution description

This PR is a splitt-off from PR #17841 and replaces partially PR #18247.

To allow the compilation for RISC-V based ESP32x SoCs, platform independent implementation of tread_arch.c, irq_arch.c and exception.c are required that are provided by a platform-specific module esp_riscv.

Additionally, some DEBUG message formatting are fixed with this PR to become platform independent.

This PR includes PR #18259 at the moment to be compilable. The first commit of this PR is d05dacd. Once PR #18529 is merged, it will be rebased.

Background:

• The file thread_arch.c in module esp_xtensa is not really independent of the used ESP SoC. Although ESP8266 and ESP32 share most of the code, they require some SoC specific code, especially in thread_yield_* functions. These functions are something very special to ESP SoCs and not common for Xtensa cores.
• We have to use vectors.S for for RISC-V interrupt handling and portasm.S for RISC-V context switching from ESP-IDF, because they are needed by other ESP-IDF functions, e.g. by the startup function, which we also use directly from ESP-IDF. Unfortunately, they are not compatible with the RISC-V implementation in cpu/riscv_common. They use a different context frame structure, a different interrupt context structure, a different interrupt/exception handling and a different startup function. Even if we could reuse some parts of riscv_common, including a common folder in the compilation always means all or nothing. Therefore we can't use cpu/riscv_common at all.
• Another problem is that the implementation of irq_disable/irq_restore in riscv_common only reset/set the MIE bit in mstatus register while the implementation for RISC-V based ESPs requires to change the value of the SoC specific interrupt level register INTERRUPT_CORE0_CPU_INT_THRESH_REG.

Thus, neither is the Xtensa code general enough to justify a cpu/xtensa_common folder, nor are the thread or interrupt handling for RISC-V based ESP compatible with the implementation in riscv_common. Therefore thread_arch.c, irq_arch.c and exception.c for Xtensa-based and RISC-V-based ESP SoCs are provided by the modules esp_xtensa and esp_riscv respectively.

Testing procedure

1. Green CI
2. Compile and check any simple test app, for example:

   BOARD=esp32-wroom-32 make -j8 -C tests/shell flash term
   

Issues/PRs references

Splitt-off from PR #17841 and PR #18247
Replaces PR #18247 partially
Depends on PR #18259

[gschorcht]

Rebased after merge of PR #18259.

[benpicco]

Please squash

[gschorcht]

@benpicco I had to rebase this PR due to a conflict with the changes in in Kconfig in PR #18314.

[gschorcht]

@benpicco Thanks for reviewing and merging.