cpu/esp32: platform independent code for thread_arch, irq_arch and exception

[gschorcht]

Contribution description

This PR is a splitt-off from PR #17841. It provides a platform independent implementation of thread_arch.c, irq_arch.c and exception.c so that it can be used for Xtensa-based and RISC-V based ESP32x SoC variants.

For that purpose the platform dependent code is moved from thread_arch.c, irq_arch.c, exception.c to thread_arch_xtensa.c, irq_arch_xtensa.c, exception_xtensa.c and thread_arch_riscv.c, irq_arch_riscv.c, exception.c_riscv, respectively. Furthermore, some DEBUG messages are fixed to be platform independent.

Background:

• The file thread_arch_xtensa.c is not really independent of the used ESP SoC. Although ESP8266 and ESP32 share most of the code, that's why thread_arch_xtensa.c is defined in cpu/esp_common, they require some SoC specific code, especially in thread_yield_* functions. These functions are something very special to ESP SoCs and not common for Xtensa cores.
• We have to use vectors.S for for RISC-V interrupt handling and portasm.S for RISC-V context switching from ESP-IDF, because they are needed by other ESP-IDF functions, e.g. by the startup function, which we also use directly from ESP-IDF. Unfortunately, they are not compatible with the RISC-V implementation in cpu/riscv_common. They use a different context frame structure, a different interrupt context structure, a different interrupt/exception handling and a different startup function. Even if we could reuse some parts of riscv_common, including a common folder in the compilation always means all or nothing. Therefore we can't use cpu/riscv_common at all.
• Another problem is that the implementation of irq_disable/irq_restore in riscv_common only reset/set the MIE bit in mstatus register while the implementation for RISC-V based ESPs requires to change the value of the SoC specific interrupt level register INTERRUPT_CORE0_CPU_INT_THRESH_REG.

Thus, neither is the Xtensa code general enough to justify a cpu/xtensa_common folder, nor are the thread or interrupt handling for RISC-V based ESP compatible with the implementation in riscv_common.
Therefore, thread_arch.c, irq_arch.c, exception.c to thread_arch_xtensa.c, irq_arch_xtensa.c, exception_xtensa.c and thread_arch_riscv.c, irq_arch_riscv.c, exception.c_riscv, respectively.

Testing procedure

1. Green CI
2. Compile and check any simple test app, for example:

   BOARD=esp32-wroom-32 make -j8 -C tests/shell flash term
   

Issues/PRs references

Split-off from PR #17841

[gschorcht]

If necessary, the PR could be split into seperate PRs.

[gschorcht]

@benpicco The PR still seems to have a lot of changes, but

• thread_arch_xtensa.c is just the code that has been removed from thread_arch.c.
• irq_arch_xtensa.c is just the code that has been removed from irq_arch.c.
• exception_xtensa.c is just the former exception.c.

The files thread_arch_riscv.c, irq_arch_riscv.c and exception_riscv.c are new.

If it helps, I could further split this PR into two PRs, one with the changes that move platform dependent code to the platform dependent files *_xtensa.c and one which adds the platform dependent files *_riscv.c.

The changes in cpu/esp32/* are the changes to use ESP-IDF HAL for interrupt handling and could also be split-off into a separate PR.

[gschorcht]

Closed in favor of PRs #18259, #18260 and #18261