cpu/stm32/periph: Implement GPIO LL for STM32F1 without IRQ support (yet) #19407

maribu · 2023-03-17T18:05:43Z

Contribution description

This implements GPIO LL support for the STM32F1 in the first commit. IRQ support is added with #19412.

This sneaks in a second commit replacing the expect() calls in tests/periph_gpio_ll with a trivial five-liner that doesn't panic(), so that stdio output will still be delivered on high level stdio implementations. The tests provides a lot of useful output to aid debugging, so its a great usability improvement if the test makes sure to actually deliver that output.

Testing procedure

make -C tests/periph_gpio_ll BOARD=nucleo-f103rb flash term

2023-03-17 18:55:09,188 # Help: Press s to start test, r to print it is ready
s
2023-03-17 18:55:10,299 # START
2023-03-17 18:55:10,307 # main(): This is RIOT! (Version: 2023.04-devel-683-g9c3812-cpu/stm32/periph/gpio_ll)
2023-03-17 18:55:10,309 # Test / Hardware Details:
2023-03-17 18:55:10,310 # ========================
2023-03-17 18:55:10,311 # Cabling:
2023-03-17 18:55:10,313 # (INPUT -- OUTPUT)
2023-03-17 18:55:10,315 #   P2.10 (PC10) -- P2.2 (PC2)
2023-03-17 18:55:10,318 #   P2.12 (PC12) -- P2.3 (PC3)
2023-03-17 18:55:10,322 # Number of pull resistor values supported: 1
2023-03-17 18:55:10,325 # Number of drive strengths supported: 1
2023-03-17 18:55:10,328 # Number of slew rates supported: 3
2023-03-17 18:55:10,330 # Valid GPIO ports:
2023-03-17 18:55:10,332 # - PORT 0 (PORT A)
2023-03-17 18:55:10,333 # - PORT 1 (PORT B)
2023-03-17 18:55:10,335 # - PORT 2 (PORT C)
2023-03-17 18:55:10,336 # - PORT 3 (PORT D)
2023-03-17 18:55:10,338 # - PORT 4 (PORT E)
2023-03-17 18:55:10,338 # 
2023-03-17 18:55:10,341 # Testing gpio_port_pack_addr()
2023-03-17 18:55:10,343 # =============================
2023-03-17 18:55:10,343 # 
2023-03-17 18:55:10,344 # All OK
2023-03-17 18:55:10,344 # 
2023-03-17 18:55:10,346 # Testing gpip_ng_init()
2023-03-17 18:55:10,348 # ======================
2023-03-17 18:55:10,348 # 
2023-03-17 18:55:10,354 # Testing is_gpio_port_num_valid() is true for PORT_OUT and PORT_IN:
2023-03-17 18:55:10,354 # 
2023-03-17 18:55:10,358 # Testing input configurations for PIN_IN_0:
2023-03-17 18:55:10,361 # Support for input with pull up: yes
2023-03-17 18:55:10,366 # state: in, pull: up, schmitt trigger: off, value: on
2023-03-17 18:55:10,369 # Support for input with pull down: yes
2023-03-17 18:55:10,374 # state: in, pull: down, schmitt trigger: off, value: off
2023-03-17 18:55:10,378 # Support for input with pull to bus level: no
2023-03-17 18:55:10,383 # Support for floating input (no pull resistors): yes
2023-03-17 18:55:10,388 # state: in, pull: none, schmitt trigger: off, value: off
2023-03-17 18:55:10,388 # 
2023-03-17 18:55:10,392 # Testing output configurations for PIN_OUT_0:
2023-03-17 18:55:10,397 # Support for output (push-pull) with initial value of LOW: yes
2023-03-17 18:55:10,401 # state: out-pp, slew: slowest, value: off
2023-03-17 18:55:10,404 # Output is indeed LOW: yes
2023-03-17 18:55:10,408 # state: out-pp, slew: slowest, value: on
2023-03-17 18:55:10,411 # Output can be pushed HIGH: yes
2023-03-17 18:55:10,417 # Support for output (push-pull) with initial value of HIGH: yes
2023-03-17 18:55:10,420 # state: out-pp, slew: slowest, value: on
2023-03-17 18:55:10,424 # Output is indeed HIGH: yes
2023-03-17 18:55:10,430 # Support for output (open drain with pull up) with initial value of LOW: no
2023-03-17 18:55:10,437 # Support for output (open drain with pull up) with initial value of HIGH: no
2023-03-17 18:55:10,443 # Support for output (open drain) with initial value of LOW: yes
2023-03-17 18:55:10,449 # state: out-od, slew: slowest, pull: none, schmitt trigger: off, value: off
2023-03-17 18:55:10,452 # Output is indeed LOW: yes
2023-03-17 18:55:10,458 # Support for output (open drain) with initial value of HIGH: yes
2023-03-17 18:55:10,465 # state: out-od, slew: slowest, pull: none, schmitt trigger: off, value: on
2023-03-17 18:55:10,470 # state: in, pull: down, schmitt trigger: off, value: off
2023-03-17 18:55:10,474 # Output can indeed be pulled LOW: yes
2023-03-17 18:55:10,478 # state: in, pull: up, schmitt trigger: off, value: on
2023-03-17 18:55:10,483 # Output can indeed be pulled HIGH: yes
2023-03-17 18:55:10,488 # Support for output (open source) with initial value of LOW: no
2023-03-17 18:55:10,494 # Support for output (open source) with initial value of HIGH: no
2023-03-17 18:55:10,501 # Support for output (open source with pull up) with initial value of HIGH: no
2023-03-17 18:55:10,508 # Support for output (open source with pull up) with initial value of LOW: no
2023-03-17 18:55:10,511 # Support for disconnecting GPIO: yes
2023-03-17 18:55:10,515 # Output can indeed be pulled LOW: yes
2023-03-17 18:55:10,519 # Output can indeed be pulled HIGH: yes
2023-03-17 18:55:10,519 # 
2023-03-17 18:55:10,523 # Testing Reading/Writing GPIO Ports
2023-03-17 18:55:10,526 # ==================================
2023-03-17 18:55:10,526 # 
2023-03-17 18:55:10,529 # testing initial value of 0 after init
2023-03-17 18:55:10,531 # ...OK
2023-03-17 18:55:10,535 # testing setting both outputs_optional simultaneously
2023-03-17 18:55:10,537 # ...OK
2023-03-17 18:55:10,541 # testing clearing both outputs_optional simultaneously
2023-03-17 18:55:10,543 # ...OK
2023-03-17 18:55:10,547 # testing toggling first output (0 --> 1)
2023-03-17 18:55:10,548 # ...OK
2023-03-17 18:55:10,552 # testing toggling first output (1 --> 0)
2023-03-17 18:55:10,553 # ...OK
2023-03-17 18:55:10,557 # testing toggling second output (0 --> 1)
2023-03-17 18:55:10,558 # ...OK
2023-03-17 18:55:10,562 # testing toggling second output (1 --> 0)
2023-03-17 18:55:10,563 # ...OK
2023-03-17 18:55:10,569 # testing setting first output and clearing second with write
2023-03-17 18:55:10,570 # ...OK
2023-03-17 18:55:10,575 # testing setting second output and clearing first with write
2023-03-17 18:55:10,576 # ...OK
2023-03-17 18:55:10,580 # All input/output operations worked as expected
2023-03-17 18:55:10,580 # 
2023-03-17 18:55:10,580 # 
2023-03-17 18:55:10,582 # TEST SUCCEEDED
2023-03-17 18:55:10,588 # { "threads": [{ "name": "main", "stack_size": 1536, "stack_used": 456 }]}

make -C tests/bench_periph_gpio_ll BOARD=nucleo-f103rb flash term

2023-03-17 18:55:42,192 # Help: Press s to start test, r to print it is ready
s
2023-03-17 18:55:44,616 # START
2023-03-17 18:55:44,624 # main(): This is RIOT! (Version: 2023.04-devel-683-g9c3812-cpu/stm32/periph/gpio_ll)
2023-03-17 18:55:44,624 # 
2023-03-17 18:55:44,626 # Benchmarking GPIO APIs
2023-03-17 18:55:44,628 # ======================
2023-03-17 18:55:44,628 # 
2023-03-17 18:55:44,632 # estimating loop overhead for compensation
2023-03-17 18:55:44,635 # -----------------------------------------
2023-03-17 18:55:44,642 # 4168 us for 50000 iterations
2023-03-17 18:55:44,642 # 
2023-03-17 18:55:44,647 # periph/gpio: Using 2x gpio_set() and 2x gpio_clear()
2023-03-17 18:55:44,651 # ---------------------------------------------------
2023-03-17 18:55:44,706 # 50000 iterations took 45840 us (50008 us uncompensated)
2023-03-17 18:55:44,713 # Two square waves pins at      1090750 Hz (      999840 Hz uncompensated)
2023-03-17 18:55:44,719 # ~66 CPU cycles per square wave period (~72 cycles uncompensated)
2023-03-17 18:55:44,719 # :'-(
2023-03-17 18:55:44,719 # 
2023-03-17 18:55:44,724 # periph/gpio_ll: Using gpio_ll_set() and gpio_ll_clear()
2023-03-17 18:55:44,729 # -------------------------------------------------------
2023-03-17 18:55:44,738 # 50000 iterations took 695 us (4863 us uncompensated)
2023-03-17 18:55:44,745 # Two square waves pins at     71942446 Hz (    10281719 Hz uncompensated)
2023-03-17 18:55:44,750 # ~1 CPU cycles per square wave period (~7 cycles uncompensated)
2023-03-17 18:55:44,751 # :-D
2023-03-17 18:55:44,751 # 
2023-03-17 18:55:44,755 # periph/gpio: Using 4x gpio_toggle()
2023-03-17 18:55:44,757 # -----------------------------------
2023-03-17 18:55:44,965 # 50000 iterations took 198646 us (202814 us uncompensated)
2023-03-17 18:55:44,972 # Two square waves pins at       251704 Hz (      246531 Hz uncompensated)
2023-03-17 18:55:44,977 # ~286 CPU cycles per square wave period (~292 cycles uncompensated)
2023-03-17 18:55:44,978 # :'-(
2023-03-17 18:55:44,978 # 
2023-03-17 18:55:44,982 # periph/gpio_ll: Using 2x gpio_ll_toggle()
2023-03-17 18:55:44,985 # -----------------------------------------
2023-03-17 18:55:45,010 # 50000 iterations took 15972 us (20140 us uncompensated)
2023-03-17 18:55:45,017 # Two square waves pins at      3130478 Hz (     2482621 Hz uncompensated)
2023-03-17 18:55:45,023 # ~23 CPU cycles per square wave period (~29 cycles uncompensated)
2023-03-17 18:55:45,023 # :'-(
2023-03-17 18:55:45,023 # 
2023-03-17 18:55:45,026 # periph/gpio: Using 4x gpio_write()
2023-03-17 18:55:45,029 # ----------------------------------
2023-03-17 18:55:45,097 # 50000 iterations took 58345 us (62513 us uncompensated)
2023-03-17 18:55:45,103 # Two square waves pins at       856971 Hz (      799833 Hz uncompensated)
2023-03-17 18:55:45,109 # ~84 CPU cycles per square wave period (~90 cycles uncompensated)
2023-03-17 18:55:45,109 # :'-(
2023-03-17 18:55:45,110 # 
2023-03-17 18:55:45,113 # periph/gpio_ll: Using 2x gpio_ll_write()
2023-03-17 18:55:45,117 # ----------------------------------------
2023-03-17 18:55:45,128 # 50000 iterations took 2777 us (6945 us uncompensated)
2023-03-17 18:55:45,135 # Two square waves pins at     18005041 Hz (     7199424 Hz uncompensated)
2023-03-17 18:55:45,141 # ~4 CPU cycles per square wave period (~10 cycles uncompensated)
2023-03-17 18:55:45,141 # :-)
2023-03-17 18:55:45,141 # 
2023-03-17 18:55:45,141 # 
2023-03-17 18:55:45,142 # TEST SUCCEEDED
2023-03-17 18:55:45,149 # { "threads": [{ "name": "main", "stack_size": 1536, "stack_used": 448 }]}

Issues/PRs references

None

riot-ci · 2023-03-17T18:06:58Z

Murdock results

✔️ PASSED

ff727f8 tests/periph_gpio_ll: Minor improvement

Success	Failures	Total	Runtime
6882	0	6882	10m:15s

Artifacts

Documentation preview

maribu · 2023-03-17T18:32:31Z

Looks like the F4 vendor headers have a GPIO_BRR_BR0 defined despite not having a BRR register in GPIO_TypeDef. For all other families this works.

Let's see if STMicroelectronics/cmsis-device-f4#7 gets merged to fix this detection. Until then, a work around can be added.

cpu/stm32/include/periph/cpu_gpio_ll.h

cpu/stm32/include/periph/f1/periph_cpu.h

gschorcht

Looks good, just a small change.

cpu/stm32/periph/gpio_ll.c

gschorcht · 2023-03-20T10:10:17Z

The test fails with a nucleo-f130rb board

Testing Reading/Writing GPIO Ports
==================================

testing initial value of 0 after init
expect failed at line 533

All tests before succeed so there shouldnt be a wiring problem.

cpu/stm32/include/periph/cpu_gpio_ll.h

maribu · 2023-03-20T11:12:12Z

The test fails with a nucleo-f130rb board

Interesting. Before, I tested with

Cabling:
(INPUT -- OUTPUT)
  P2.10 (PC10) -- P2.2 (PC2)
  P2.12 (PC12) -- P2.3 (PC3)

which succeeded (and still does now). I thought that maybe using the same port for both input and output results in a bug not being triggered, so I tested

Cabling:
(INPUT -- OUTPUT)
  P2.10 (PC10) -- P3.0 (PD0)
  P2.12 (PC12) -- P3.1 (PD1)

which failed at

Testing output configurations for PIN_OUT_0:
Support for output (push-pull) with initial value of LOW: yes
state: out-pp, slew: slowest, value: off
Output is indeed LOW: yes
state: out-pp, slew: slowest, value: on
Output can be pushed HIGH: no
expect failed at line 205

Finally I ran the test again with

Cabling:
(INPUT -- OUTPUT)
  P2.10 (PC10) -- P1.8 (PB8)
  P2.12 (PC12) -- P1.9 (PB9)

which again succeeded.

It looks like PD0 and PD1 are connected to the high speed crystal, which caused the issues. Maybe you also just got unlikely by picking a pin that is connected to a crystal, LED or button?

I'm using this saved as Makefile.nucleo-f103rb:

cat Makefile.nucleo-f103rb 
PORT_IN ?= 2
PORT_OUT ?= 1
PIN_IN_0 ?= 10
PIN_IN_1 ?= 12
PIN_OUT_0 ?= 8
PIN_OUT_1 ?= 9

gschorcht · 2023-03-20T13:01:23Z

Maybe you also just got unlikely by picking a pin that is connected to a crystal, LED or button?

Yeah, I used the default configuration where PB1 is used which is connected to AVDD by default with solder bridge for this board 🙈

Ok, I can confirm that the test works.

gschorcht · 2023-03-20T13:02:02Z

Please squash.

maribu · 2023-03-20T13:13:18Z

Sorry, I added the IRQ support after the ACK. I will split out the IRQ support into a separate PR and squash the rest, one moment.

This provides basic GPIO LL support. IRQ support will be added as follow up.

Use a custom expect() that just spins in an endless loop instead of panicking. The test isn't run automatically anyway, as it requires connecting two GPIOs with jumper wires; but when run manually it is helpful to not kill RIOT to also get the stdio output of the exact point where the test fails (e.g. USB CDC ACM doesn't like panic()).

gschorcht · 2023-03-20T13:16:01Z

cpu/stm32/periph/gpio_ll_irq.c

+#endif
+
+#if defined(EXTI_C2_BASE)
+#  define EXTI_REG_IMR        (EXTI_C2->IMR1)


Ok, that makes it more readable, but do our coding conventions allow indentation for preprocessor definitions?

There are a few instances where this is done and I couldn't find anything that forbids it. This is not too nested here, so the benefit of the indent is not that large here. E.g. in

RIOT/sys/include/ztimer/config.h

Lines 39 to 55 in 9b34769

#if CONFIG_ZTIMER_USEC_TYPE_PERIPH_TIMER

# ifndef CONFIG_ZTIMER_USEC_DEV

# ifdef XTIMER_DEV

# define CONFIG_ZTIMER_USEC_DEV XTIMER_DEV

# endif

# endif

# ifndef CONFIG_ZTIMER_USEC_BASE_FREQ

# ifdef XTIMER_HZ

# define CONFIG_ZTIMER_USEC_BASE_FREQ XTIMER_HZ

# endif

# endif

# ifndef CONFIG_ZTIMER_USEC_WIDTH

# ifdef XTIMER_WIDTH

# define CONFIG_ZTIMER_USEC_WIDTH XTIMER_WIDTH

# endif

# endif

#endif

without the indent I would be lost :D So if you prefer without the indent, I could drop it. (But I have moved this now to #19412)

Yes, I saw that a while ago as well. I am absolutely fine with it. Plain nested preprocessor #ifndef chains really make the code unreadable. I was just wondering because I remember a discussion we both had when I was trying to structure nested preprocessor conditionals 😉

gschorcht · 2023-03-20T13:17:19Z

If you prefer you could also add IRQ support.

gschorcht · 2023-03-20T15:14:06Z

bors merge

bors · 2023-03-20T17:20:10Z

Build succeeded:

maribu · 2023-03-20T17:30:07Z

Thx :)

19412: cpu/stm32/periph: Add GPIO LL IRQ support for STM32F1 r=gschorcht a=maribu ### Contribution description As the title says ### Testing procedure <details><summary><code>make BOARD=nucleo-f103rb flash test-with-config -C tests/periph_gpio_ll</code></summary> ``` make: Entering directory '/home/maribu/Repos/software/RIOT/tests/periph_gpio_ll' Building application "tests_periph_gpio_ll" for "nucleo-f103rb" with MCU "stm32". "make" -C /home/maribu/Repos/software/RIOT/boards/common/init "make" -C /home/maribu/Repos/software/RIOT/boards/nucleo-f103rb "make" -C /home/maribu/Repos/software/RIOT/boards/common/nucleo "make" -C /home/maribu/Repos/software/RIOT/core "make" -C /home/maribu/Repos/software/RIOT/core/lib "make" -C /home/maribu/Repos/software/RIOT/cpu/stm32 "make" -C /home/maribu/Repos/software/RIOT/cpu/cortexm_common "make" -C /home/maribu/Repos/software/RIOT/cpu/cortexm_common/periph "make" -C /home/maribu/Repos/software/RIOT/cpu/stm32/periph "make" -C /home/maribu/Repos/software/RIOT/cpu/stm32/stmclk "make" -C /home/maribu/Repos/software/RIOT/cpu/stm32/vectors "make" -C /home/maribu/Repos/software/RIOT/drivers "make" -C /home/maribu/Repos/software/RIOT/drivers/periph_common "make" -C /home/maribu/Repos/software/RIOT/sys "make" -C /home/maribu/Repos/software/RIOT/sys/auto_init "make" -C /home/maribu/Repos/software/RIOT/sys/div "make" -C /home/maribu/Repos/software/RIOT/sys/frac "make" -C /home/maribu/Repos/software/RIOT/sys/isrpipe "make" -C /home/maribu/Repos/software/RIOT/sys/libc "make" -C /home/maribu/Repos/software/RIOT/sys/malloc_thread_safe "make" -C /home/maribu/Repos/software/RIOT/sys/newlib_syscalls_default "make" -C /home/maribu/Repos/software/RIOT/sys/pm_layered "make" -C /home/maribu/Repos/software/RIOT/sys/preprocessor "make" -C /home/maribu/Repos/software/RIOT/sys/stdio_uart "make" -C /home/maribu/Repos/software/RIOT/sys/test_utils/interactive_sync "make" -C /home/maribu/Repos/software/RIOT/sys/test_utils/print_stack_usage "make" -C /home/maribu/Repos/software/RIOT/sys/tsrb "make" -C /home/maribu/Repos/software/RIOT/sys/ztimer text data bss dec hex filename 20760 176 2728 23664 5c70 /home/maribu/Repos/software/RIOT/tests/periph_gpio_ll/bin/nucleo-f103rb/tests_periph_gpio_ll.elf /home/maribu/Repos/software/RIOT/dist/tools/openocd/openocd.sh flash /home/maribu/Repos/software/RIOT/tests/periph_gpio_ll/bin/nucleo-f103rb/tests_periph_gpio_ll.elf ### Flashing Target ### Open On-Chip Debugger 0.12.0+dev-snapshot (2023-03-13-08:56) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html DEPRECATED! use 'adapter serial' not 'hla_serial' hla_swd Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD srst_only separate srst_nogate srst_open_drain connect_assert_srst Info : clock speed 1000 kHz Info : STLINK V2J29M18 (API v2) VID:PID 0483:374B Info : Target voltage: 3.252984 Info : [stm32f1x.cpu] Cortex-M3 r1p1 processor detected Info : [stm32f1x.cpu] target has 6 breakpoints, 4 watchpoints Info : starting gdb server for stm32f1x.cpu on 0 Info : Listening on port 32843 for gdb connections TargetName Type Endian TapName State -- ------------------ ---------- ------ ------------------ ------------ 0* stm32f1x.cpu hla_target little stm32f1x.cpu unknown [stm32f1x.cpu] halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x08001ae4 msp: 0x20000200 Info : device id = 0x20036410 Info : flash size = 128 KiB Warn : Adding extra erase range, 0x080051c8 .. 0x080053ff auto erase enabled wrote 20936 bytes from file /home/maribu/Repos/software/RIOT/tests/periph_gpio_ll/bin/nucleo-f103rb/tests_periph_gpio_ll.elf in 1.192543s (17.144 KiB/s) verified 20936 bytes in 0.333379s (61.328 KiB/s) shutdown command invoked Done flashing r /home/maribu/Repos/software/RIOT/dist/tools/pyterm/pyterm -p "/dev/ttyACM1" -b "115200" --no-reconnect --noprefix --no-repeat-command-on-empty-line Connect to serial port /dev/ttyACM1 Welcome to pyterm! Type '/exit' to exit. READY s START main(): This is RIOT! (Version: 2023.04-devel-685-gd0d5d-cpu/stm32/periph/gpio_ll_irq) Test / Hardware Details: ======================== Cabling: (INPUT -- OUTPUT) P2.10 (PC10) -- P1.8 (PB8) P2.12 (PC12) -- P1.9 (PB9) Number of pull resistor values supported: 1 Number of drive strengths supported: 1 Number of slew rates supported: 4 Valid GPIO ports: - PORT 0 (PORT A) - PORT 1 (PORT B) - PORT 2 (PORT C) - PORT 3 (PORT D) - PORT 4 (PORT E) Testing gpio_port_pack_addr() ============================= All OK Testing gpip_ng_init() ====================== Testing is_gpio_port_num_valid() is true for PORT_OUT and PORT_IN: Testing input configurations for PIN_IN_0: Support for input with pull up: yes state: in, pull: up, schmitt trigger: off, value: on Support for input with pull down: yes state: in, pull: down, schmitt trigger: off, value: off Support for input with pull to bus level: no Support for floating input (no pull resistors): yes state: in, pull: none, schmitt trigger: off, value: off Testing output configurations for PIN_OUT_0: Support for output (push-pull) with initial value of LOW: yes state: out-pp, slew: slowest, value: off Output is indeed LOW: yes state: out-pp, slew: slowest, value: on Output can be pushed HIGH: yes Support for output (push-pull) with initial value of HIGH: yes state: out-pp, slew: slowest, value: on Output is indeed HIGH: yes Support for output (open drain with pull up) with initial value of LOW: no Support for output (open drain with pull up) with initial value of HIGH: no Support for output (open drain) with initial value of LOW: yes state: out-od, slew: slowest, pull: none, schmitt trigger: off, value: off Output is indeed LOW: yes Support for output (open drain) with initial value of HIGH: yes state: out-od, slew: slowest, pull: none, schmitt trigger: off, value: on state: in, pull: down, schmitt trigger: off, value: off Output can indeed be pulled LOW: yes state: in, pull: up, schmitt trigger: off, value: on Output can indeed be pulled HIGH: yes Support for output (open source) with initial value of LOW: no Support for output (open source) with initial value of HIGH: no Support for output (open source with pull up) with initial value of HIGH: no Support for output (open source with pull up) with initial value of LOW: no Support for disconnecting GPIO: yes Output can indeed be pulled LOW: yes Output can indeed be pulled HIGH: yes Testing Reading/Writing GPIO Ports ================================== testing initial value of 0 after init ...OK testing setting both outputs_optional simultaneously ...OK testing clearing both outputs_optional simultaneously ...OK testing toggling first output (0 --> 1) ...OK testing toggling first output (1 --> 0) ...OK testing toggling second output (0 --> 1) ...OK testing toggling second output (1 --> 0) ...OK testing setting first output and clearing second with write ...OK testing setting second output and clearing first with write ...OK All input/output operations worked as expected Testing External IRQs ===================== Testing rising edge on PIN_IN_0 ... OK Testing falling edge on PIN_IN_0 ... OK Testing both edges on PIN_IN_0 ... OK Testing masking of IRQs (still both edges on PIN_IN_0) ... OK Testing level-triggered on HIGH on PIN_IN_0 (when input is LOW when setting up IRQ) ... OK Testing level-triggered on HIGH on PIN_IN_0 (when input is HIGH when setting up IRQ) ... OK Testing level-triggered on LOW on PIN_IN_0 (when input is HIGH when setting up IRQ) ... OK Testing level-triggered on LOW on PIN_IN_0 (when input is LOW when setting up IRQ) ... OK TEST SUCCEEDED ``` </details> ### Issues/PRs references Depends on #19407 Co-authored-by: Marian Buschsieweke <[email protected]>

19454: cpu/stm32/periph_gpio_ll: Fix misleading comments r=gschorcht a=maribu ### Contribution description The comments still claim STM32F1 support is missing, but this was recently added. Also, drop an empty line to fix `too many consecutive empty lines` nitpick of the CI. ### Testing procedure This since only changes comments, this won't effect the binaries. Technically, those comments would be Doxygen compatible comments. But as only Doxygen comments in headers are parsed, these are in practice regular plain comments. ### Issues/PRs references #19407 added basic GPIO LL support for STM32F1, #19412 added the IRQ support on top of that. Co-authored-by: Marian Buschsieweke <[email protected]>

19268: shell_lock: don't set CONFIG_SHELL_SHUTDOWN_ON_EXIT r=benpicco a=benpicco 19629: cpu/stm32/periph/adc: fix setting ADC clock r=benpicco a=Enoch247 ### Contribution description The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability. I based on code similarity. I believe the gd32v CPU may need this same fix, but I am not familiar with that MCU. ### Testing procedure I tested this on a nucleo-f767zi. The the MCU's reference manual is in agreement with what I have implemented here. I spot checked references manuals for a random [STM32F1](https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf) and [STM32F2](https://www.st.com/resource/en/reference_manual/rm0033-stm32f205xx-stm32f207xx-stm32f215xx-and-stm32f217xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf), and they are clocked similar to the F7 I have. ### Issues/PRs references None known. 19670: cpu/stm32: stm32f4 BRR from BSRR r=benpicco a=kfessel ### Contribution description sometimes one wants to save one instruction :) just write the bits we need to write. ### Testing procedure tests/periph/gpio_ll tests this ### Issues/PRs references `@maribu` might know some reference maybe #19407 Co-authored-by: Benjamin Valentin <[email protected]> Co-authored-by: Benjamin Valentin <[email protected]> Co-authored-by: Joshua DeWeese <[email protected]> Co-authored-by: Karl Fessel <[email protected]>

19629: cpu/stm32/periph/adc: fix setting ADC clock r=benpicco a=Enoch247 ### Contribution description The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability. I based on code similarity. I believe the gd32v CPU may need this same fix, but I am not familiar with that MCU. ### Testing procedure I tested this on a nucleo-f767zi. The the MCU's reference manual is in agreement with what I have implemented here. I spot checked references manuals for a random [STM32F1](https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf) and [STM32F2](https://www.st.com/resource/en/reference_manual/rm0033-stm32f205xx-stm32f207xx-stm32f215xx-and-stm32f217xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf), and they are clocked similar to the F7 I have. ### Issues/PRs references None known. 19670: cpu/stm32: stm32f4 BRR from BSRR r=benpicco a=kfessel ### Contribution description sometimes one wants to save one instruction :) just write the bits we need to write. ### Testing procedure tests/periph/gpio_ll tests this ### Issues/PRs references `@maribu` might know some reference maybe #19407 Co-authored-by: Joshua DeWeese <[email protected]> Co-authored-by: Karl Fessel <[email protected]>

19610: drivers/periph/rtc: improve doc on rtc_set_alarm r=maribu a=maribu ### Contribution description - point out behavior on denormalized time stamps - use errno codes to indicate errors (and adapt the few instances of actual error handling to use them) 19670: cpu/stm32: stm32f4 BRR from BSRR r=maribu a=kfessel ### Contribution description sometimes one wants to save one instruction :) just write the bits we need to write. ### Testing procedure tests/periph/gpio_ll tests this ### Issues/PRs references `@maribu` might know some reference maybe #19407 19678: gnrc_sixlowpan_iphc: fix NULL pointer dereference r=maribu a=miri64 19679: gnrc_sixlowpan_frag_sfr: fix ARQ scheduler race-condition r=maribu a=miri64 19680: gnrc_sixlowpan_frag_rb: fix OOB write in _rbuf_add r=maribu a=miri64 19681: sys/xtimer: improve documentation r=maribu a=maribu ### Contribution description - Add a warning that xtimer is deprecated, so that new code hopefully starts using ztimer - Add a hint that `ztimer_xtimer_compat` can be used even after `xtimer` is gone Co-authored-by: Marian Buschsieweke <[email protected]> Co-authored-by: Karl Fessel <[email protected]> Co-authored-by: Martine Lenders <[email protected]>

maribu added Type: new feature The issue requests / The PR implemements a new feature for RIOT CI: ready for build If set, CI server will compile all applications for all available boards for the labeled PR Area: cpu Area: CPU/MCU ports labels Mar 17, 2023

maribu requested review from smlng, leandrolanzieri, aabadie, MichelRottleuthner, fjmolinas, DipSwitch and vincent-d as code owners March 17, 2023 18:05

github-actions bot added Area: tests Area: tests and testing framework Platform: ARM Platform: This PR/issue effects ARM-based platforms labels Mar 17, 2023

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maribu requested review from jia200x and MrKevinWeiss as code owners March 20, 2023 13:10

maribu changed the title ~~cpu/stm32/periph: Implement GPIO LL for STM32F1 (no IRQ yet)~~ cpu/stm32/periph: Implement GPIO LL for STM32F1 Mar 20, 2023

github-actions bot added the Area: Kconfig Area: Kconfig integration label Mar 20, 2023

maribu added 2 commits March 20, 2023 14:14

cpu/stm32: Implement gpio_ll for STM32F1

4a0c462

This provides basic GPIO LL support. IRQ support will be added as follow up.

maribu force-pushed the cpu/stm32/periph/gpio_ll branch from 6cba180 to ff727f8 Compare March 20, 2023 13:14

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cpu/stm32/periph: Add GPIO LL IRQ support for STM32F1 #19412

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maribu changed the title ~~cpu/stm32/periph: Implement GPIO LL for STM32F1~~ cpu/stm32/periph: Implement GPIO LL for STM32F1 without IRQ support (yet) Mar 20, 2023

bors bot merged commit 45c839d into RIOT-OS:master Mar 20, 2023

maribu deleted the cpu/stm32/periph/gpio_ll branch March 20, 2023 17:30

maribu mentioned this pull request Apr 5, 2023

cpu/stm32/periph_gpio_ll: Fix misleading comments #19454

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MrKevinWeiss added this to the Release 2023.04 milestone Apr 25, 2023

kfessel mentioned this pull request May 25, 2023

cpu/stm32: stm32f4 BRR from BSRR #19670

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cpu/stm32/periph: Implement GPIO LL for STM32F1 without IRQ support (yet) #19407

cpu/stm32/periph: Implement GPIO LL for STM32F1 without IRQ support (yet) #19407

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	#if CONFIG_ZTIMER_USEC_TYPE_PERIPH_TIMER
	# ifndef CONFIG_ZTIMER_USEC_DEV
	# ifdef XTIMER_DEV
	# define CONFIG_ZTIMER_USEC_DEV XTIMER_DEV
	# endif
	# endif
	# ifndef CONFIG_ZTIMER_USEC_BASE_FREQ
	# ifdef XTIMER_HZ
	# define CONFIG_ZTIMER_USEC_BASE_FREQ XTIMER_HZ
	# endif
	# endif
	# ifndef CONFIG_ZTIMER_USEC_WIDTH
	# ifdef XTIMER_WIDTH
	# define CONFIG_ZTIMER_USEC_WIDTH XTIMER_WIDTH
	# endif
	# endif
	#endif

cpu/stm32/periph: Implement GPIO LL for STM32F1 without IRQ support (yet) #19407

cpu/stm32/periph: Implement GPIO LL for STM32F1 without IRQ support (yet) #19407

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