cpu/stm32: stm32f4 BRR from BSRR #19670
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kfessel
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maribu
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That should indeed save an instruction. Previously the compiler would take the GPIO port base address
- add the offset of the BSRR register
- do a left shift
- do a 32 bit store
Now it would take the GPIO port base address
- add the offest of the BSRR register + 2
- do a 16 bit store
Please fix the style nitpicks and squash directly
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19268: shell_lock: don't set CONFIG_SHELL_SHUTDOWN_ON_EXIT r=benpicco a=benpicco 19629: cpu/stm32/periph/adc: fix setting ADC clock r=benpicco a=Enoch247 ### Contribution description The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability. I based on code similarity. I believe the gd32v CPU may need this same fix, but I am not familiar with that MCU. ### Testing procedure I tested this on a nucleo-f767zi. The the MCU's reference manual is in agreement with what I have implemented here. I spot checked references manuals for a random [STM32F1](https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf) and [STM32F2](https://www.st.com/resource/en/reference_manual/rm0033-stm32f205xx-stm32f207xx-stm32f215xx-and-stm32f217xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf), and they are clocked similar to the F7 I have. ### Issues/PRs references None known. 19670: cpu/stm32: stm32f4 BRR from BSRR r=benpicco a=kfessel ### Contribution description sometimes one wants to save one instruction :) just write the bits we need to write. ### Testing procedure tests/periph/gpio_ll tests this ### Issues/PRs references `@maribu` might know some reference maybe #19407 Co-authored-by: Benjamin Valentin <[email protected]> Co-authored-by: Benjamin Valentin <[email protected]> Co-authored-by: Joshua DeWeese <[email protected]> Co-authored-by: Karl Fessel <[email protected]>
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19629: cpu/stm32/periph/adc: fix setting ADC clock r=benpicco a=Enoch247 ### Contribution description The current implementation uses the core clock frequency to calculate the needed prescalar to achieve a given ADC clock frequency. This is incorrect. This patch fixes the calculation to use the correct source clock (PCKLK2 ie APB2). It also changes the defined max clock rate to use the frequency macro to improve readability. I based on code similarity. I believe the gd32v CPU may need this same fix, but I am not familiar with that MCU. ### Testing procedure I tested this on a nucleo-f767zi. The the MCU's reference manual is in agreement with what I have implemented here. I spot checked references manuals for a random [STM32F1](https://www.st.com/resource/en/reference_manual/cd00171190-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf) and [STM32F2](https://www.st.com/resource/en/reference_manual/rm0033-stm32f205xx-stm32f207xx-stm32f215xx-and-stm32f217xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf), and they are clocked similar to the F7 I have. ### Issues/PRs references None known. 19670: cpu/stm32: stm32f4 BRR from BSRR r=benpicco a=kfessel ### Contribution description sometimes one wants to save one instruction :) just write the bits we need to write. ### Testing procedure tests/periph/gpio_ll tests this ### Issues/PRs references `@maribu` might know some reference maybe #19407 Co-authored-by: Joshua DeWeese <[email protected]> Co-authored-by: Karl Fessel <[email protected]>
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cpu/stm32/include/gpio_ll_arch.h
Outdated
| @@ -77,7 +77,8 @@ static inline void gpio_ll_clear(gpio_port_t port, uword_t mask) | |||
| #if defined(GPIO_BRR_BR0) && !defined(CPU_FAM_STM32F4) | |||
| p->BRR = mask; | |||
| #else | |||
| p->BSRR = mask << 16; | |||
| uint16_t *brr = (void *)&(p->BSRR); | |||
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Suggested change
| uint16_t *brr = (void *)&(p->BSRR); | |
| volatile uint16_t *brr = (volatile uint16_t *)&(p->BSRR); |
The volatile is needed here and C++ is being annoying again here.
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I was so free to add this. Should be good to go now.
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19610: drivers/periph/rtc: improve doc on rtc_set_alarm r=maribu a=maribu ### Contribution description - point out behavior on denormalized time stamps - use errno codes to indicate errors (and adapt the few instances of actual error handling to use them) 19670: cpu/stm32: stm32f4 BRR from BSRR r=maribu a=kfessel ### Contribution description sometimes one wants to save one instruction :) just write the bits we need to write. ### Testing procedure tests/periph/gpio_ll tests this ### Issues/PRs references `@maribu` might know some reference maybe #19407 19678: gnrc_sixlowpan_iphc: fix NULL pointer dereference r=maribu a=miri64 19679: gnrc_sixlowpan_frag_sfr: fix ARQ scheduler race-condition r=maribu a=miri64 19680: gnrc_sixlowpan_frag_rb: fix OOB write in _rbuf_add r=maribu a=miri64 19681: sys/xtimer: improve documentation r=maribu a=maribu ### Contribution description - Add a warning that xtimer is deprecated, so that new code hopefully starts using ztimer - Add a hint that `ztimer_xtimer_compat` can be used even after `xtimer` is gone Co-authored-by: Marian Buschsieweke <[email protected]> Co-authored-by: Karl Fessel <[email protected]> Co-authored-by: Martine Lenders <[email protected]>
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Contribution description
sometimes one wants to save one instruction :)
just write the bits we need to write.
Testing procedure
tests/periph/gpio_ll tests this
Issues/PRs references
@maribu might know some reference
maybe #19407