RISC-V Support SE-148 #234
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…ency, rather than update the VCT register to total cycles completed.
…m register (PMCCNTR_EL0 for Aarch64).
A fix for handling missing system registers in the aarch64 systemRegisterMap_ map. A missing entry will return a -1 and a decoded instruction accessing an unmapped system register will raise a new UnmappedSysReg fatal exception.
…ow for a wider param space (#229)
Fixes output error present for miniBUDE when compiled with GCC-10.3.0 targeting armv8.4-a+sve, caused by an incorrect implementation of the FNEG sve instruction. Additionally, other SVE instructions were updated to accomodate for optional patterns.
…e Linux machines.
A new generic branch predictor containing parameterisable BTB and RAS structures, global indexing, and better identification of branch instructions. Additionally, a parameterisable loop buffer has been implemented in the fetch unit and a loop detection scheme in the ROB unit.
…tions. Also added the ability to define ISA extensions to target as a parameter to the parent regression class run function
…enmp codes. Current additions omit functionality as it's not required for the codes to execute correctly.
jj16791
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Oct 28, 2022
jj16791
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Nov 3, 2022
FinnWilkinson
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Nov 4, 2022
jj16791
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Nov 7, 2022
rahahahat
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Nov 7, 2022
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#rerun tests |
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#rerun tests |
rahahahat
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Nov 24, 2022
jj16791
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Nov 25, 2022
FinnWilkinson
requested changes
Nov 28, 2022
FinnWilkinson
approved these changes
Nov 28, 2022
rahahahat
approved these changes
Nov 28, 2022
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This pull request adds support for rv64iam. That is, 64 bit RISC-V base, atomic and multiply extensions working in all three simulation modes. Expanding on previous work, the general code base has been adjusted to be more ISA agnostic. Specific config option parsing has been moved to the ISA specific classes and the exception handler has become more generic. Some more work may be needed on this as exception types are currently ISA specific; this causes the need for repeated functions which is undesirable. Almost all of the base, atomic and multiply extension instructions have been implemented along with their pseudoinstructions. ### Architecture updates - rv64i - RISC-V base extension - a - RISC-V atomic extension - m - RISC-V multiply/divide extension ### Changes to config options - Addition of ```ISA``` option with valid arguments <```aarch64```, ```rv64```> ### To note - FENCE is implemented as a NOP which is considered allowable by the spec - EBREAK is unimplemented but only needed for debugging - Atomics don't operate truly atomically which is currently functional for single threaded programs but not accurate - MULH and MULHSU aren't implemented as they will need a library such as GMP. Tests are implemented and expected to fail This functionality is sufficient to run many benchmarks including STREAM, Dhrystone and an implementation of the Smith-Waterman algorithm.
jj16791
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that referenced
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May 19, 2023
This pull request adds support for rv64iam. That is, 64 bit RISC-V base, atomic and multiply extensions working in all three simulation modes. Expanding on previous work, the general code base has been adjusted to be more ISA agnostic. Specific config option parsing has been moved to the ISA specific classes and the exception handler has become more generic. Some more work may be needed on this as exception types are currently ISA specific; this causes the need for repeated functions which is undesirable. Almost all of the base, atomic and multiply extension instructions have been implemented along with their pseudoinstructions. ### Architecture updates - rv64i - RISC-V base extension - a - RISC-V atomic extension - m - RISC-V multiply/divide extension ### Changes to config options - Addition of ```ISA``` option with valid arguments <```aarch64```, ```rv64```> ### To note - FENCE is implemented as a NOP which is considered allowable by the spec - EBREAK is unimplemented but only needed for debugging - Atomics don't operate truly atomically which is currently functional for single threaded programs but not accurate - MULH and MULHSU aren't implemented as they will need a library such as GMP. Tests are implemented and expected to fail This functionality is sufficient to run many benchmarks including STREAM, Dhrystone and an implementation of the Smith-Waterman algorithm.
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This pull request adds support for rv64iam. That is 64 bit RISC-V base, atomic and multiply extensions working in all three simulation modes.
Expanding on previous work, the general code base has been adjusted to be more ISA agnostic. Specific config option parsing has been moved to the ISA specific classes and the exception handler has become more generic. Some more work may be needed on this as exception types are currently ISA specific; this causes the need for repeated functions which is undesirable.
Almost all of the base, atomic and multiply extension instructions have been implemented along with their pseudoinstructions. To note:
FENCE is implemented as a NOP which is considered allowable by the spec
EBREAK is unimplemented but only needed for debugging
Atomics don't operate truly atomically which is currently functional for single threaded programs but not accurate
MULH and MULHSU aren't implemented as they will need a library such as GMP. Tests are implemented and expected to fail
This functionality is sufficient to run many benchmarks including STREAM, Dhrystone and an implementation of the Smith-Waterman algorithm.