New core creation

configs/a64fx.yaml

@@ -37,7 +37,11 @@ Branch-Predictor:
   Global-History-Length: 11
   RAS-entries: 8
   Fallback-Static-Predictor: "Always-Taken"
-L1-Cache:
+L1-Data-Memory:
+  Interface-Type: Fixed
+L1-Instruction-Memory:
+  Interface-Type: Flat
+LSQ-L1-Interface:
   Access-Latency: 5
   Exclusive: True
   Load-Bandwidth: 128
@@ -239,9 +243,9 @@ Latencies:
 # CPU-Info mainly used to generate a replica of the special (or system) file directory 
 # structure
 CPU-Info:
-  # Set Generate-Special-Dir to 'T' to generate the special files directory, or to 'F' to not.
+  # Set Generate-Special-Dir to True to generate the special files directory, or to False to not.
   # (Not generating the special files directory may require the user to copy over files manually)
-  Generate-Special-Dir: T
+  Generate-Special-Dir: True
   # Core-Count MUST be 1 as multi-core is not supported at this time. (A64FX true value is 48)
   Core-Count: 1
   # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (A64FX true value is 1)

configs/m1_firestorm.yaml

@@ -29,8 +29,12 @@ Branch-Predictor:
   Saturating-Count-Bits: 2  
   Global-History-Length: 11 
   RAS-entries: 8 
-  Fallback-Static-Predictor: "Always-Taken" 
-L1-Cache:
+  Fallback-Static-Predictor: "Always-Taken"
+L1-Data-Memory:
+  Interface-Type: Fixed
+L1-Instruction-Memory:
+  Interface-Type: Flat
+LSQ-L1-Interface:
   Access-Latency: 3
   Exclusive: False
   L1 Load Bandwidth: 48
@@ -277,17 +281,27 @@ Latencies:
       - SCALAR
     Execution-Latency: 3
     Execution-Throughput: 1
+# CPU-Info mainly used to generate a replica of the special (or system) file directory 
+# structure
 CPU-Info:
-  Generate-Special-Dir: T
+  # Set Generate-Special-Dir to True to generate the special files directory, or to False to not.
+  # (Not generating the special files directory may require the user to copy over files manually)
+  Generate-Special-Dir: True
+  # Core-Count MUST be 1 as multi-core is not supported at this time. (A64FX true value is 48)
   Core-Count: 1
+  # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (A64FX true value is 1)
   Socket-Count: 1
+  # SMT MUST be 1 as Simultanious-Multi-Threading is not supported at this time. (A64FX true value is 1)
   SMT: 1
+  # Below are the values needed to generate /proc/cpuinfo
   BogoMIPS: 48.00
   Features: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint
   CPU-Implementer: "0x46"
   CPU-Architecture: 8
   CPU-Variant: "0x1"
   CPU-Part: "0x001"
   CPU-Revision: 0
+  # Package-Count is used to generate 
+  # /sys/devices/system/cpu/cpu{0..Core-Count}/topology/{physical_package_id, core_id}
   Package-Count: 1
 

configs/tx2.yaml

@@ -35,7 +35,11 @@ Branch-Predictor:
   Global-History-Length: 10
   RAS-entries: 5
   Fallback-Static-Predictor: "Always-Taken"
-L1-Cache:
+L1-Data-Memory:
+  Interface-Type: Fixed
+L1-Instruction-Memory:
+  Interface-Type: Flat
+LSQ-L1-Interface:
   Access-Latency: 4
   Exclusive: False
   Load-Bandwidth: 32
@@ -159,9 +163,9 @@ Latencies:
 # CPU-Info mainly used to generate a replica of the special (or system) file directory 
 # structure
 CPU-Info:
-  # Set Generate-Special-Dir to 'T' to generate the special files directory, or to 'F' to not.
+  # Set Generate-Special-Dir to True to generate the special files directory, or to False to not.
   # (Not generating the special files directory may require the user to copy over files manually)
-  Generate-Special-Dir: T
+  Generate-Special-Dir: True
   # Core-Count MUST be 1 as multi-core is not supported at this time. (TX2 true value is 32)
   Core-Count: 1
   # Socket-Count MUST be 1 as multi-socket simulations are not supported at this time. (TX2 true value is 2)

src/include/simeng/BranchPredictor.hh

@@ -5,6 +5,7 @@
 
 namespace simeng {
 
+/** The types of branches recognised. */
 enum class BranchType {
   Conditional = 0,
   LoopClosing,

src/include/simeng/CoreInstance.hh

@@ -0,0 +1,163 @@
+#pragma once
+
+#include <string>
+
+#include "simeng/AlwaysNotTakenPredictor.hh"
+#include "simeng/Core.hh"
+#include "simeng/Elf.hh"
+#include "simeng/FixedLatencyMemoryInterface.hh"
+#include "simeng/FlatMemoryInterface.hh"
+#include "simeng/GenericPredictor.hh"
+#include "simeng/ModelConfig.hh"
+#include "simeng/SpecialFileDirGen.hh"
+#include "simeng/arch/Architecture.hh"
+#include "simeng/arch/aarch64/Architecture.hh"
+#include "simeng/arch/aarch64/Instruction.hh"
+#include "simeng/arch/aarch64/MicroDecoder.hh"
+#include "simeng/kernel/Linux.hh"
+#include "simeng/models/emulation/Core.hh"
+#include "simeng/models/inorder/Core.hh"
+#include "simeng/models/outoforder/Core.hh"
+#include "simeng/pipeline/A64FXPortAllocator.hh"
+#include "simeng/pipeline/BalancedPortAllocator.hh"
+#include "yaml-cpp/yaml.h"
+
+// Program used when no executable is provided; counts down from
+// 1024*1024, with an independent `orr` at the start of each branch.
+uint32_t hex_[] = {
+    0x320C03E0,  // orr w0, wzr, #1048576
+    0x320003E1,  // orr w0, wzr, #1
+    0x71000400,  // subs w0, w0, #1
+    0x54FFFFC1,  // b.ne -8
+                 // .exit:
+    0xD2800000,  // mov x0, #0
+    0xD2800BC8,  // mov x8, #94
+    0xD4000001,  // svc #0
+};
+
+namespace simeng {
+
+/** The available modes of simulation. */
+enum class SimulationMode { Emulation, InOrderPipelined, OutOfOrder };
+
+/** A class to create a SimEng core instance from a supplied config. */
+class CoreInstance {
+ public:
+  /** Default constructor with an executable and its arguments but no model
+   * configuration. */
+  CoreInstance(std::string executablePath,
+               std::vector<std::string> executableArgs);
+
+  /** Constructor with an executable, its arguments, and a model configuration.
+   */
+  CoreInstance(std::string configPath, std::string executablePath,
+               std::vector<std::string> executableArgs);
+
+  ~CoreInstance();
+
+  /** Set the SimEng L1 instruction cache memory. */
+  void setL1InstructionMemory(std::shared_ptr<simeng::MemoryInterface> memRef);
+
+  /** Set the SimEng L1 data cache memory. */
+  void setL1DataMemory(std::shared_ptr<simeng::MemoryInterface> memRef);
+
+  /** Construct the core and all its associated simulation objects after the
+   * process and memory interfaces have been instantiated. */
+  void createCore();
+
+  /** Getter for the set simulation mode. */
+  const SimulationMode getSimulationMode() const;
+
+  /** Getter for the set simulation mode in a string format. */
+  const std::string getSimulationModeString() const;
+
+  /** Getter for the create core object. */
+  std::shared_ptr<simeng::Core> getCore() const;
+
+  /** Getter for the create data memory object. */
+  std::shared_ptr<simeng::MemoryInterface> getDataMemory() const;
+
+  /** Getter for the create instruction memory object. */
+  std::shared_ptr<simeng::MemoryInterface> getInstructionMemory() const;
+
+  /** Getter for a shared pointer to the created process image. */
+  std::shared_ptr<char> getProcessImage() const;
+
+  /** Getter for the size of the created process image. */
+  const uint64_t getProcessImageSize() const;
+
+ private:
+  /** Generate the appropriate simulation objects as parameterised by the
+   * configuration.*/
+  void generateCoreModel(std::string executablePath,
+                         std::vector<std::string> executableArgs);
+
+  /** Extract simulation mode from config file. */
+  void setSimulationMode();
+
+  /** Construct the SimEng linux process object from command line arguments.
+   * Empty command line arguments denote the usage of hardcoded
+   * instructions held in the hex_ array. */
+  void createProcess(std::string executablePath,
+                     std::vector<std::string> executableArgs);
+
+  /** Construct the process memory from the generated process_ object. */
+  void createProcessMemory();
+
+  /** Construct the SimEng L1 instruction cache memory. */
+  void createL1InstructionMemory(const simeng::MemInterfaceType type);
+
+  /** Construct the SimEng L1 data cache memory. */
+  void createL1DataMemory(const simeng::MemInterfaceType type);
+
+  /** Construct the special file directory. */
+  void createSpecialFileDirectory();
+
+  /** The config file describing the modelled core to be created. */
+  YAML::Node config_;
+
+  /** Reference to the SimEng linux process object. */
+  std::unique_ptr<simeng::kernel::LinuxProcess> process_ = nullptr;
+
+  /** The size of the process memory. */
+  uint64_t processMemorySize_;
+
+  /** The process memory space. */
+  std::shared_ptr<char> processMemory_;
+
+  /** The SimEng Linux kernel object. */
+  simeng::kernel::Linux kernel_;
+
+  /** Whether or not the dataMemory_ must be set manually. */
+  bool setDataMemory_ = false;
+
+  /** Whether or not the instructionMemory_ must be set manually. */
+  bool setInstructionMemory_ = false;
+
+  /** Reference to the SimEng architecture object. */
+  std::unique_ptr<simeng::arch::Architecture> arch_ = nullptr;
+
+  /** Reference to the SimEng branch predictor object. */
+  std::unique_ptr<simeng::BranchPredictor> predictor_ = nullptr;
+
+  /** Reference to the SimEng port allocator object. */
+  std::unique_ptr<simeng::pipeline::PortAllocator> portAllocator_ = nullptr;
+
+  /** Reference to the SimEng core object. */
+  std::shared_ptr<simeng::Core> core_ = nullptr;
+
+  /** The simulation mode in use, defaulting to emulation. */
+  SimulationMode mode_ = SimulationMode::Emulation;
+
+  /** A string format for the simulation mode in use, defaulting to emulation.
+   */
+  std::string modeString_ = "Emulation";
+
+  /** Reference to the SimEng data memory object. */
+  std::shared_ptr<simeng::MemoryInterface> dataMemory_ = nullptr;
+
+  /** Reference to the SimEng instruction memory object. */
+  std::shared_ptr<simeng::MemoryInterface> instructionMemory_ = nullptr;
+};
+
+}  // namespace simeng

src/include/simeng/MemoryInterface.hh

@@ -5,6 +5,14 @@
 
 namespace simeng {
 
+/** The available memory interface types. */
+enum class MemInterfaceType {
+  Flat,     // A zero access latency interface
+  Fixed,    // A fixed, non-zero, access latency interface
+  External  // An interface generated outside of the standard SimEng
+            // instantiation
+};
+
 /** A generic memory access target; describes a region of memory to access. */
 struct MemoryAccessTarget {
   /** The address to access. */

src/include/simeng/ModelConfig.hh

@@ -14,32 +14,34 @@
 #include "simeng/arch/aarch64/Instruction.hh"
 #include "yaml-cpp/yaml.h"
 
-#define DEFAULT_CONFIG                                                        \
-  ("{Core: {Simulation-Mode: inorderpipelined, Clock-Frequency: 2.5, "        \
-   "Timer-Frequency: 100, Micro-Operations: True, Vector-Length: 512}, "      \
-   "Fetch: {Fetch-Block-Size: 32, Loop-Buffer-Size: 64, "                     \
-   "Loop-Detection-Threshold: 4}, Process-Image: {Heap-Size: 10485760, "      \
-   "Stack-Size: 1048576}, Register-Set: {GeneralPurpose-Count: 154, "         \
-   "FloatingPoint/SVE-Count: 90, Predicate-Count: 17, Conditional-Count: "    \
-   "128}, Pipeline-Widths: {Commit: 4, Dispatch-Rate: 4, FrontEnd: 4, "       \
-   "LSQ-Completion: 2}, Queue-Sizes: {ROB: 180, Load: 64, Store: 36}, "       \
-   "Branch-Predictor: {BTB-Tag-Bits: 11, Saturating-Count-Bits: 2, "          \
-   "Global-History-Length: 10, RAS-entries: 5, Fallback-Static-Predictor: "   \
-   "2}, L1-Cache: {Access-Latency: 4, Exclusive: False, Load-Bandwidth: 32, " \
-   "Store-Bandwidth: 16, Permitted-Requests-Per-Cycle: 2, "                   \
-   "Permitted-Loads-Per-Cycle: 2, Permitted-Stores-Per-Cycle: 1}, Ports: "    \
-   "{'0': {Portname: Port 0, Instruction-Group-Support: [1, 8, 14]}, '1': "   \
-   "{Portname: Port 1, Instruction-Group-Support: [0, 14]}, '2': {Portname: " \
-   "Port 2, Instruction-Group-Support: [1, 8, 71]}, '3': {Portname: Port 4, " \
-   "Instruction-Group-Support: [67]}, '4': {Portname: Port 5, "               \
-   "Instruction-Group-Support: [67]}, '5': {Portname: Port 3, "               \
-   "Instruction-Group-Support: [70]}}, Reservation-Stations: {'0': {Size: "   \
-   "60, Ports: [0, 1, 2, 3, 4, 5]}}, Execution-Units: {'0': {Pipelined: "     \
-   "true}, '1': {Pipelined: true}, '2': {Pipelined: true}, '3': {Pipelined: " \
-   "true}, '4': {Pipelined: true}, '5': {Pipelined: true}}, CPU-Info: "       \
-   "{Generate-Special-Dir: F, Core-Count: 1, Socket-Count: 1, SMT: 1, "       \
-   "BogoMIPS: 200.00, Features: fp asimd evtstrm atomics cpuid, "             \
-   "CPU-Implementer: 0x0, CPU-Architecture: 0, CPU-Variant: 0x0, CPU-Part: "  \
+#define DEFAULT_CONFIG                                                         \
+  ("{Core: {Simulation-Mode: inorderpipelined, Clock-Frequency: 2.5, "         \
+   "Timer-Frequency: 100, Micro-Operations: True, Vector-Length: 512}, "       \
+   "Fetch: {Fetch-Block-Size: 32, Loop-Buffer-Size: 64, "                      \
+   "Loop-Detection-Threshold: 4}, Process-Image: {Heap-Size: 10485760, "       \
+   "Stack-Size: 1048576}, Register-Set: {GeneralPurpose-Count: 154, "          \
+   "FloatingPoint/SVE-Count: 90, Predicate-Count: 17, Conditional-Count: "     \
+   "128}, Pipeline-Widths: {Commit: 4, Dispatch-Rate: 4, FrontEnd: 4, "        \
+   "LSQ-Completion: 2}, Queue-Sizes: {ROB: 180, Load: 64, Store: 36}, "        \
+   "Branch-Predictor: {BTB-Tag-Bits: 11, Saturating-Count-Bits: 2, "           \
+   "Global-History-Length: 10, RAS-entries: 5, Fallback-Static-Predictor: "    \
+   "2}, L1-Data-Memory: {Interface-Type: Flat}, L1-Instruction-Memory: "       \
+   "{Interface-Type: Flat}, LSQ-L1-Interface: {Access-Latency: 4, Exclusive: " \
+   "False, Load-Bandwidth: 32, Store-Bandwidth: 16, "                          \
+   "Permitted-Requests-Per-Cycle: 2, Permitted-Loads-Per-Cycle: 2, "           \
+   "Permitted-Stores-Per-Cycle: 1}, Ports: {'0': {Portname: Port 0, "          \
+   "Instruction-Group-Support: [1, 8, 14]}, '1': {Portname: Port 1, "          \
+   "Instruction-Group-Support: [0, 14]}, '2': {Portname: Port 2, "             \
+   "Instruction-Group-Support: [1, 8, 71]}, '3': {Portname: Port 4, "          \
+   "Instruction-Group-Support: [67]}, '4': {Portname: Port 5, "                \
+   "Instruction-Group-Support: [67]}, '5': {Portname: Port 3, "                \
+   "Instruction-Group-Support: [70]}}, Reservation-Stations: {'0': {Size: "    \
+   "60, Ports: [0, 1, 2, 3, 4, 5]}}, Execution-Units: {'0': {Pipelined: "      \
+   "true}, '1': {Pipelined: true}, '2': {Pipelined: true}, '3': "              \
+   "{Pipelined:true}, '4': {Pipelined: true}, '5': {Pipelined: true}}, "       \
+   "CPU-Info: {Generate-Special-Dir: false, Core-Count: 1, Socket-Count: 1, "  \
+   "SMT: 1, BogoMIPS: 200.00, Features: fp asimd evtstrm atomics cpuid, "      \
+   "CPU-Implementer: 0x0, CPU-Architecture: 0, CPU-Variant: 0x0, CPU-Part: "   \
    "0x0, CPU-Revision: 0, Package-Count: 1}}")
 
 namespace simeng {

src/include/simeng/arch/Architecture.hh

@@ -14,6 +14,7 @@ using MacroOp = std::vector<std::shared_ptr<Instruction>>;
 
 namespace arch {
 
+/** The types of changes that can be made to values within the process state. */
 enum class ChangeType { REPLACEMENT, INCREMENT, DECREMENT };
 
 /** A structure describing a set of changes to the process state. */

src/include/simeng/arch/aarch64/Instruction.hh

@@ -174,6 +174,7 @@ struct ExecutionInfo {
   std::vector<uint8_t> ports = {};
 };
 
+/** The various exceptions that can be raised by an individual instruction. */
 enum class InstructionException {
   None = 0,
   EncodingUnallocated,

src/include/simeng/models/inorder/Core.hh

@@ -20,7 +20,7 @@ class Core : public simeng::Core {
   /** Construct a core model, providing an ISA and branch predictor to use,
    * along with a pointer and size of instruction memory, and a pointer to
    * process memory. */
-  Core(FlatMemoryInterface& instructionMemory, FlatMemoryInterface& dataMemory,
+  Core(MemoryInterface& instructionMemory, MemoryInterface& dataMemory,
        uint64_t processMemorySize, uint64_t entryPoint,
        const arch::Architecture& isa, BranchPredictor& branchPredictor);
 

src/include/simeng/pipeline/FetchUnit.hh

@@ -9,6 +9,7 @@
 namespace simeng {
 namespace pipeline {
 
+/** The various states of the loop buffer. */
 enum class LoopBufferState {
   IDLE = 0,  // No operations
   WAITING,   // Waiting to find boundary instruction in fetch stream

src/include/simeng/pipeline/LoadStoreQueue.hh

@@ -13,6 +13,7 @@
 namespace simeng {
 namespace pipeline {
 
+/** The memory access types which are processed. */
 enum accessType { LOAD = 0, STORE };
 
 /** A requestQueue_ entry. */

src/lib/CMakeLists.txt

@@ -28,6 +28,7 @@ set(SIMENG_SOURCES
     AlwaysNotTakenPredictor.cc
     ArchitecturalRegisterFileSet.cc
     CMakeLists.txt
+    CoreInstance.cc
     Elf.cc
     FixedLatencyMemoryInterface.cc
     FlatMemoryInterface.cc
@@ -37,7 +38,7 @@ set(SIMENG_SOURCES
     RegisterFileSet.cc
     RegisterValue.cc
     SpecialFileDirGen.cc
-    )
+)
 
 configure_file(${capstone_SOURCE_DIR}/arch/AArch64/AArch64GenInstrInfo.inc AArch64GenInstrInfo.inc COPYONLY)