Fix DesignTools.makePhysNetNamesConsistent() (#703)

* Add test for #701 Signed-off-by: Eddie Hung <[email protected]> * Update testcase and test Signed-off-by: Eddie Hung <[email protected]> * Add testMakePhysNetNamesConsistentLogicalVccGnd() Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() By transforming logical static nets <const{0,1}> into physical static nets GLOBAL_LOGIC{0,1} Signed-off-by: Eddie Hung <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestDesignTools.java Signed-off-by: eddieh-xlnx <[email protected]> * Improve testcase, check against Vivado only if present Signed-off-by: Eddie Hung <[email protected]> * Update RapidWrightDCP Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]>
Xilinx · Jun 16, 2023 · 555732b · 555732b
1 parent cd8923c
commit 555732b
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Showing 4 changed files with 66 additions and 3 deletions.
diff --git a/src/com/xilinx/rapidwright/design/DesignTools.java b/src/com/xilinx/rapidwright/design/DesignTools.java
@@ -2799,7 +2799,17 @@ public static void makePhysNetNamesConsistent(Design design) {
                 continue;
             }
             if (!hierNet.equals(parentHierNet)) {
-                Net parentPhysNet = design.getNet(parentHierNet.getHierarchicalNetName());
+                String parentHierNetName = parentHierNet.getHierarchicalNetName();
+                Net parentPhysNet;
+                if (parentHierNetName.equals(EDIFTools.LOGICAL_VCC_NET_NAME)) {
+                    parentHierNetName = Net.VCC_NET;
+                    parentPhysNet = design.getVccNet();
+                } else if (parentHierNetName.equals(EDIFTools.LOGICAL_GND_NET_NAME)) {
+                    parentHierNetName = Net.GND_NET;
+                    parentPhysNet = design.getGndNet();
+                } else {
+                    parentPhysNet = design.getNet(parentHierNetName);
+                }
                 if (parentPhysNet != null) {
                     // Merge both physical nets together
                     for (SiteInst si : net.getSiteInsts()) {
@@ -2811,7 +2821,7 @@ public static void makePhysNetNamesConsistent(Design design) {
                         }
                     }
                     design.movePinsToNewNetDeleteOldNet(net, parentPhysNet, true);
-                } else if (!net.rename(parentHierNet.getHierarchicalNetName())) {
+                } else if (!net.rename(parentHierNetName)) {
                     System.out.println("WARNING: Failed to adjust physical net name " + net.getName());
                 }
             }

diff --git a/test/RapidWrightDCP b/test/RapidWrightDCP
diff --git a/test/src/com/xilinx/rapidwright/design/TestDesignTools.java b/test/src/com/xilinx/rapidwright/design/TestDesignTools.java
@@ -948,4 +948,35 @@ public void testCreateCeSrRstPinsToVCC(String deviceName, String location, Strin
             Assertions.assertEquals(vcc, spi.getNet());
         }
     }
+
+    @Test
+    public void testMakePhysNetNamesConsistentLogicalVccGnd() {
+        Design design = RapidWrightDCP.loadDCP("bug701.dcp");
+
+        // Design has no GLOBAL_LOGIC{0,1}
+        Assertions.assertNull(design.getNet(Net.VCC_NET));
+        Assertions.assertNull(design.getNet(Net.GND_NET));
+
+        DesignTools.makePhysNetNamesConsistent(design);
+
+        // Check those nets were created and all sitewires
+        // were switched over correctly
+        Net vcc = design.getNet(Net.VCC_NET);
+        Assertions.assertNotNull(vcc);
+        Assertions.assertEquals(1, vcc.getSiteInsts().size());
+        int numSitewires = 0;
+        for (SiteInst si : vcc.getSiteInsts()) {
+            numSitewires += si.getSiteWiresFromNet(vcc).size();
+        }
+        Assertions.assertEquals(1, numSitewires);
+
+        Net gnd = design.getNet(Net.GND_NET);
+        Assertions.assertNotNull(gnd);
+        Assertions.assertEquals(4, gnd.getSiteInsts().size());
+        numSitewires = 0;
+        for (SiteInst si : gnd.getSiteInsts()) {
+            numSitewires += si.getSiteWiresFromNet(gnd).size();
+        }
+        Assertions.assertEquals(31, numSitewires);
+    }
 }
diff --git a/test/src/com/xilinx/rapidwright/rwroute/TestRWRoute.java b/test/src/com/xilinx/rapidwright/rwroute/TestRWRoute.java
@@ -258,4 +258,26 @@ public void testRWRouteDeviceSupport(Series series) {
             break;
         }
     }
+
+    @Test
+    public void testBug701() {
+        Design design = RapidWrightDCP.loadDCP("bug701.dcp");
+
+        RWRoute.routeDesignFullNonTimingDriven(design);
+
+        Net vcc = design.getVccNet();
+        Assertions.assertEquals(1, vcc.getPins().size());
+        Assertions.assertTrue(vcc.getPins().stream().allMatch(SitePinInst::isRouted));
+
+        Net gnd = design.getGndNet();
+        Assertions.assertEquals(31, gnd.getPins().size());
+        Assertions.assertTrue(gnd.getPins().stream().allMatch(SitePinInst::isRouted));
+
+        if (FileTools.isVivadoOnPath()) {
+            // Testcase has a number of undriven nets, so just check for unrouted nets
+            ReportRouteStatusResult rrs = VivadoTools.reportRouteStatus(design);
+            Assertions.assertEquals(0, rrs.unroutedNets);
+        }
+    }
+
 }