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RWRoute only assigns a single SitePinInst to the ground net. #701
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Hi @haydenc-amd. I'm not able to reproduce what you're seeing. This is my log on the latest commit (74ed97f):
Loading the routed design into Vivado and doing Are you seeing something different? |
@eddieh-xlnx when I run
Additionally, when I load the routed design in Vivado and run
Running I made sure to pull from master and ran |
@eddieh-xlnx I accidentally uploaded a version of the counter that didn't have any flip flops. I don't know why, but when the checkpoint doesn't have FFs, it seems to route GND and VCC just fine. Here is the checkpoint with FFs. Sorry for the troubles! |
Signed-off-by: Eddie Hung <[email protected]>
Signed-off-by: Eddie Hung <[email protected]>
* Add testcase for Xilinx/RapidWright#701 * Correct testcase
* Add test for #701 Signed-off-by: Eddie Hung <[email protected]> * Update testcase and test Signed-off-by: Eddie Hung <[email protected]> * Add testMakePhysNetNamesConsistentLogicalVccGnd() Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() By transforming logical static nets <const{0,1}> into physical static nets GLOBAL_LOGIC{0,1} Signed-off-by: Eddie Hung <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestDesignTools.java Signed-off-by: eddieh-xlnx <[email protected]> * Improve testcase, check against Vivado only if present Signed-off-by: Eddie Hung <[email protected]> * Update RapidWrightDCP Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]>
* Add test for #701 Signed-off-by: Eddie Hung <[email protected]> * Update testcase and test Signed-off-by: Eddie Hung <[email protected]> * Add testMakePhysNetNamesConsistentLogicalVccGnd() Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() By transforming logical static nets <const{0,1}> into physical static nets GLOBAL_LOGIC{0,1} Signed-off-by: Eddie Hung <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestDesignTools.java Signed-off-by: eddieh-xlnx <[email protected]> * Improve testcase, check against Vivado only if present Signed-off-by: Eddie Hung <[email protected]> * Update RapidWrightDCP Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]>
* Add test for Xilinx#701 Signed-off-by: Eddie Hung <[email protected]> * Update testcase and test Signed-off-by: Eddie Hung <[email protected]> * Add testMakePhysNetNamesConsistentLogicalVccGnd() Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() By transforming logical static nets <const{0,1}> into physical static nets GLOBAL_LOGIC{0,1} Signed-off-by: Eddie Hung <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestDesignTools.java Signed-off-by: eddieh-xlnx <[email protected]> * Improve testcase, check against Vivado only if present Signed-off-by: Eddie Hung <[email protected]> * Update RapidWrightDCP Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]> Signed-off-by: Hayden Cook <[email protected]>
* Incremental clock router fixes Signed-off-by: Eddie Hung <[email protected]> * GlobalSignalRouting.routeStaticNet() to not clobber existing PIPs Signed-off-by: Eddie Hung <[email protected]> * Remove redundant PartialRouter.routeStaticNets() override Signed-off-by: Eddie Hung <[email protected]> * Remove import Signed-off-by: Eddie Hung <[email protected]> * Cleanup/document/refactor Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() (#703) * Add test for #701 Signed-off-by: Eddie Hung <[email protected]> * Update testcase and test Signed-off-by: Eddie Hung <[email protected]> * Add testMakePhysNetNamesConsistentLogicalVccGnd() Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() By transforming logical static nets <const{0,1}> into physical static nets GLOBAL_LOGIC{0,1} Signed-off-by: Eddie Hung <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestDesignTools.java Signed-off-by: eddieh-xlnx <[email protected]> * Improve testcase, check against Vivado only if present Signed-off-by: Eddie Hung <[email protected]> * Update RapidWrightDCP Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]> * Tidy up Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]>
* Basic incremental clock router Signed-off-by: Chris Lavin <[email protected]> * Adding comments Signed-off-by: Chris Lavin <[email protected]> * Updating whitespace Signed-off-by: Chris Lavin <[email protected]> * Fix spacing Signed-off-by: Eddie Hung <[email protected]> * UltraScale Incremental Clock Router fixes (#706) * Incremental clock router fixes Signed-off-by: Eddie Hung <[email protected]> * GlobalSignalRouting.routeStaticNet() to not clobber existing PIPs Signed-off-by: Eddie Hung <[email protected]> * Remove redundant PartialRouter.routeStaticNets() override Signed-off-by: Eddie Hung <[email protected]> * Remove import Signed-off-by: Eddie Hung <[email protected]> * Cleanup/document/refactor Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() (#703) * Add test for #701 Signed-off-by: Eddie Hung <[email protected]> * Update testcase and test Signed-off-by: Eddie Hung <[email protected]> * Add testMakePhysNetNamesConsistentLogicalVccGnd() Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() By transforming logical static nets <const{0,1}> into physical static nets GLOBAL_LOGIC{0,1} Signed-off-by: Eddie Hung <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestDesignTools.java Signed-off-by: eddieh-xlnx <[email protected]> * Improve testcase, check against Vivado only if present Signed-off-by: Eddie Hung <[email protected]> * Update RapidWrightDCP Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]> * Tidy up Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]> Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]> Co-authored-by: Eddie Hung <[email protected]>
I have an unrouted design checkpoint (shared below). When I attempted to route using RWRoute (
rapidwright RWRoute cntr-preRouted.dcp cntr-routed.dcp --nonTimingDriven
), it only routes the GND net to a single site pin leaving the rest of the net unrouted.cntr-preRouted.zip
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