Squashed commit of the following:

commit 188e6c3 Author: Chris Lavin <[email protected]> Date: Wed Jul 5 11:15:30 2023 -0600 Unroute site routing when removing a cell (#729) * Fixes an issue with makeBlackBox trying to remove pins from renamed nets Signed-off-by: Chris Lavin <[email protected]> * Adding code to properly unroute site routing of a cell when removed Signed-off-by: Chris Lavin <[email protected]> * Tweak description Signed-off-by: Chris Lavin <[email protected]> * Add test, more fixes Signed-off-by: Chris Lavin <[email protected]> * Fix test failure Signed-off-by: Chris Lavin <[email protected]> * Update src/com/xilinx/rapidwright/design/DesignTools.java Co-authored-by: eddieh-xlnx <[email protected]> Signed-off-by: Chris Lavin <[email protected]> * More fixes Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]> Co-authored-by: eddieh-xlnx <[email protected]> commit 830c4dc Author: eddieh-xlnx <[email protected]> Date: Wed Jul 5 09:07:17 2023 -0700 PartialRouter's global router to not unpreserve sink nodes (#736) * PartialRouter's global router to not unpreserve sinks nodes Signed-off-by: Eddie Hung <[email protected]> * Only disallow if input pin Signed-off-by: Eddie Hung <[email protected]> * Update comment Signed-off-by: Eddie Hung <[email protected]> * Refactor PartialRouter.getGlobalRoutingNodeStatus() Signed-off-by: Eddie Hung <[email protected]> * Remove extra char Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> commit 263cfe1 Author: eddieh-xlnx <[email protected]> Date: Thu Jun 29 14:29:52 2023 -0700 DesignTools.makePhysNetNamesConsistent() to use hier name (#735) * DesignTools.makePhysNetNamesConsisntent() to use hier name Signed-off-by: Eddie Hung <[email protected]> * Another case Signed-off-by: Eddie Hung <[email protected]> * Remove unused Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> commit 83807c9 Author: eddieh-xlnx <[email protected]> Date: Thu Jun 29 11:53:59 2023 -0700 DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734) Look at the non-hier net name to determine if GLOBAL_LOGIC{0,1} Signed-off-by: Eddie Hung <[email protected]> commit beae92f Author: zakn-amd <[email protected]> Date: Thu Jun 29 10:30:00 2023 -0700 Add DcpToInterchange class (#704) * add module to convert DCP to FPGA Interchange Signed-off-by: Zak Nafziger <[email protected]> * Tidy up, use Paths.get() not Path.of() Signed-off-by: Eddie Hung <[email protected]> * Address review comments (retry) Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Zak Nafziger <[email protected]> Signed-off-by: Eddie Hung <[email protected]> Co-authored-by: Eddie Hung <[email protected]> commit b645df4 Author: Chris Lavin <[email protected]> Date: Thu Jun 29 10:22:16 2023 -0600 Add compile step (#733) Signed-off-by: Chris Lavin <[email protected]> commit 61e0f87 Author: eddieh-xlnx <[email protected]> Date: Wed Jun 28 13:24:32 2023 -0700 Add EdifToLogicalNetlist to MainEntrypoint (#731) Signed-off-by: Eddie Hung <[email protected]> commit 671515a Author: eddieh-xlnx <[email protected]> Date: Tue Jun 27 13:14:35 2023 -0700 [PhysNetlistReader] Set Cell type for routethru cells (#727) Signed-off-by: Eddie Hung <[email protected]> commit 90e2c04 Author: Chris Lavin <[email protected]> Date: Fri Jun 23 16:40:54 2023 -0600 Fix Javadoc warnings (#723) * Fix JavaDoc warnings Signed-off-by: Chris Lavin <[email protected]> * More javadoc fixes Signed-off-by: Eddie Hung <[email protected]> * More javadoc fixes Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]> Signed-off-by: Eddie Hung <[email protected]> Co-authored-by: Eddie Hung <[email protected]> commit 92f595b Author: Chris Lavin <[email protected]> Date: Fri Jun 23 16:40:39 2023 -0600 Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728) Signed-off-by: Chris Lavin <[email protected]> commit 05ebb30 Author: Chris Lavin <[email protected]> Date: Fri Jun 23 15:08:48 2023 -0600 Multilevel macro expansion (#726) * Adds support for expanding the IOBUFDSE3 macro and OBUFTDS_DCIEN_DUAL_BUF Signed-off-by: Chris Lavin <[email protected]> * Add additional check Signed-off-by: Chris Lavin <[email protected]> --------- Signed-off-by: Chris Lavin <[email protected]> commit 7af0bc6 Author: eddieh-xlnx <[email protected]> Date: Thu Jun 22 17:00:31 2023 -0700 TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725) Signed-off-by: Eddie Hung <[email protected]> commit d4a0f1a Author: eddieh-xlnx <[email protected]> Date: Thu Jun 22 16:10:29 2023 -0700 DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724) * Create test for a site pin that is not connected to any Node-s Signed-off-by: Eddie Hung <[email protected]> * DesignTools.createMissingSitePinInsts() to skip node-less site pins Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> commit 33df8b1 Author: Chris Lavin <[email protected]> Date: Wed Jun 21 17:27:23 2023 -0600 Bump Python to 2023.1.1 Signed-off-by: Chris Lavin <[email protected]> Signed-off-by: Eddie Hung <[email protected]>
Xilinx · Jul 5, 2023 · 77f1a84 · 77f1a84
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diff --git a/README.md b/README.md
@@ -52,6 +52,7 @@ cd $RAPIDWRIGHT_PATH
 git pull
 # resolve any issues
 ./gradlew updateJars
+./gradlew compileJava
 ```
 
 ### Python Setup

diff --git a/python/setup.py b/python/setup.py
@@ -24,7 +24,7 @@
 
 setup(
     name='rapidwright',
-    version='2023.1.0',
+    version='2023.1.1',
     license='Apache 2.0 and Others',
     description='Xilinx RapidWright Framework Wrapped for Python.',
     long_description='',

diff --git a/python/src/rapidwright/rapidwright.py b/python/src/rapidwright/rapidwright.py
@@ -24,7 +24,7 @@
 from typing import List, Optional
 import os, urllib.request, platform
 
-version='2023.1.0'
+version='2023.1.1'
 
 def start_jvm():
     os_str = 'lin64'

diff --git a/src/com/xilinx/rapidwright/MainEntrypoint.java b/src/com/xilinx/rapidwright/MainEntrypoint.java
@@ -66,7 +66,9 @@
 import com.xilinx.rapidwright.examples.StampPlacement;
 import com.xilinx.rapidwright.examples.UpdateRoutingUsingSATRouter;
 import com.xilinx.rapidwright.examples.tilebrowser.PartTileBrowser;
+import com.xilinx.rapidwright.interchange.DcpToInterchange;
 import com.xilinx.rapidwright.interchange.DeviceResourcesExample;
+import com.xilinx.rapidwright.interchange.EdifToLogicalNetlist;
 import com.xilinx.rapidwright.interchange.EnumerateCellBelMapping;
 import com.xilinx.rapidwright.interchange.GenerateInterchangeDevices;
 import com.xilinx.rapidwright.interchange.Interchange;
@@ -123,6 +125,7 @@ private static void addFunction(String name, MainStyleFunction<?> func) {
         addFunction("CompareRouteStatusReports", CompareRouteStatusReports::main);
         addFunction("CopyMMCMCell", CopyMMCMCell::main);
         addFunction("CustomRouting", CustomRouting::main);
+        addFunction("DcpToInterchange", DcpToInterchange::main);
         addFunction("DecomposeLUT", DecomposeLUT::main);
         addFunction("DesignImplementationDiff", DesignImplementationDiff::main);
         addFunction("DesignInstrumentor", DesignInstrumentor::main);
@@ -132,6 +135,7 @@ private static void addFunction(String name, MainStyleFunction<?> func) {
         addFunction("EDIFNetlist", EDIFNetlist::main);
         addFunction("EDIFParser", EDIFParser::main);
         addFunction("EDIFPropertyValue", EDIFPropertyValue::main);
+        addFunction("EDIFToLogicalNetlist", EdifToLogicalNetlist::main);
         addFunction("EDIFTools", EDIFTools::main);
         addFunction("EnumerateCellBelMapping", EnumerateCellBelMapping::main);
         addFunction("ExampleNetlistCreation", ExampleNetlistCreation::main);

diff --git a/src/com/xilinx/rapidwright/design/DesignTools.java b/src/com/xilinx/rapidwright/design/DesignTools.java
diff --git a/src/com/xilinx/rapidwright/design/ModuleInst.java b/src/com/xilinx/rapidwright/design/ModuleInst.java
@@ -526,9 +526,9 @@ public Net getCorrespondingNet(Port p) {
 
 
     /**
-     * Get's the corresponding port on the module by name.
+     * Gets the corresponding port on the module by name.
      * @param name
-     * @return
+     * @return Port object.
      */
     public Port getPort(String name) {
         return module.getPort(name);

diff --git a/src/com/xilinx/rapidwright/design/merge/MergeDesigns.java b/src/com/xilinx/rapidwright/design/merge/MergeDesigns.java
@@ -33,7 +33,6 @@
 import java.util.stream.Collectors;
 import java.util.stream.Stream;
 
-
 import com.xilinx.rapidwright.design.Design;
 import com.xilinx.rapidwright.design.DesignTools;
 import com.xilinx.rapidwright.design.Net;
@@ -46,8 +45,9 @@
 import com.xilinx.rapidwright.tests.CodePerfTracker;
 
 /**
- * Merges two or more designs into a single Design.  Merge process can be customized through the
- * use of the {@link MergeOptions} class.
+ * Merges two or more designs into a single Design. Merge process can be
+ * customized through the use of the @link {@link AbstractDesignMerger}
+ * interface.
  */
 public class MergeDesigns {
 
@@ -127,8 +127,7 @@ public static Design mergeDesigns(Design...designs) {
      * netlist.  Assumes that designs are compatible for merging. Assumes that if there are duplicate
      * cells in the set of designs to be merged that they are flip-flops and that they are always
      * connected to a top-level port.
-     * @param options The set of options to customize the merge process based on netlist-specific
-     * names
+     * @param merger The specific design merger instance to use to merge the designs
      * @param designs The set of designs to be merged into a single design.
      * @return The merged design that contains the superset of all logic, placement and routing of
      * the input designs.

diff --git a/src/com/xilinx/rapidwright/design/tools/LUTTools.java b/src/com/xilinx/rapidwright/design/tools/LUTTools.java
@@ -34,6 +34,7 @@
 import com.xilinx.rapidwright.design.Design;
 import com.xilinx.rapidwright.design.Unisim;
 import com.xilinx.rapidwright.device.BEL;
+import com.xilinx.rapidwright.device.BELPin;
 import com.xilinx.rapidwright.device.Device;
 import com.xilinx.rapidwright.edif.EDIFCell;
 import com.xilinx.rapidwright.edif.EDIFCellInst;
@@ -101,7 +102,19 @@ public static String getCompanionLUTName(String lutName) {
     }
 
     /**
-     * Checks if this cell is a LUT (LUT1, LUT2, LUT3,...). A CFGLUT5 will return false.
+     * Gets the output pin from the BEL of a LUT
+     * 
+     * @param bel The physical bel site of the LUT
+     * @return O5 or O6 based on the BEL
+     */
+    public static BELPin getLUTOutputPin(BEL bel) {
+        return bel.getPin("O" + bel.getName().charAt(1));
+    }
+
+    /**
+     * Checks if this cell is a LUT (LUT1, LUT2, LUT3,...). A CFGLUT5 will return
+     * false.
+     * 
      * @param c The cell in question
      * @return True if this is a LUT[1-6], false otherwise.
      */

diff --git a/src/com/xilinx/rapidwright/edif/BinaryEDIFReader.java b/src/com/xilinx/rapidwright/edif/BinaryEDIFReader.java
@@ -66,7 +66,7 @@ private static boolean readEDIFName(EDIFName o, Input is, String[] strings) {
      * @param o The object to read
      * @param is The Kryo-based input stream
      * @param strings Indexed string lookup
-     * @see BinaryEDIFWriter#writeEDIFObject(EDIFPropertyObject, Output, Map<String,Integer>)
+     * @see BinaryEDIFWriter#writeEDIFObject(EDIFPropertyObject, Output, Map)
      */
     static void readEDIFObject(EDIFPropertyObject o, Input is, String[] strings) {
         if (readEDIFName(o, is, strings)) {

diff --git a/src/com/xilinx/rapidwright/edif/BinaryEDIFWriter.java b/src/com/xilinx/rapidwright/edif/BinaryEDIFWriter.java
@@ -156,7 +156,7 @@ private static void writeEDIFName(EDIFName o, Output os, Map<String,Integer> str
      * @param o The object write
      * @param os The Kryo-based output stream
      * @param stringMap Map of String to enumeration integers
-     * @see #readEDIFObject(EDIFPropertyObject, Output, Map)
+     * @see BinaryEDIFReader#readEDIFObject(EDIFPropertyObject, Input, String[])
      */
     private static void writeEDIFObject(EDIFPropertyObject o, Output os, Map<String,Integer> stringMap) {
         boolean hasProperties = o.getPropertiesMap().size() > 0;

diff --git a/src/com/xilinx/rapidwright/edif/EDIFCell.java b/src/com/xilinx/rapidwright/edif/EDIFCell.java
@@ -249,8 +249,8 @@ public EDIFPort addPort(EDIFPort port) {
 
     /**
      * Gets a port by bus name (see {@link EDIFPort#getBusName()}). Multi-bit ports
-     * need to have closing square bracket and range removed (for example: "bus[3:0]"
-     * -> "bus[". See {@link EDIFCell#addPort(EDIFPort)} for more information.
+     * need to have closing square bracket and range removed (for example:
+     * {@code "bus[3:0]" -> "bus["}). See {@link EDIFCell#addPort(EDIFPort)} for more information.
      *
      * @param name Bus name (ends with '[' to represent a bussed port) of the
      *                port to get. Single bit ports use their entire name.

diff --git a/src/com/xilinx/rapidwright/edif/EDIFNetlist.java b/src/com/xilinx/rapidwright/edif/EDIFNetlist.java
@@ -171,6 +171,7 @@ public class EDIFNetlist extends EDIFName {
             // Prim -> Macro (when set IOStandard matches expansion set)
             seriesMacroExpandExceptionMap.put("OBUFDS", new Pair<>("OBUFDS_DUAL_BUF", obufExpansion));
             seriesMacroExpandExceptionMap.put("OBUFTDS", new Pair<>("OBUFTDS_DUAL_BUF", obufExpansion));
+            seriesMacroExpandExceptionMap.put("OBUFTDS_DCIEN", new Pair<>("OBUFTDS_DCIEN_DUAL_BUF", obufExpansion));
             macroExpandExceptionMap.put(s, seriesMacroExpandExceptionMap);
 
             for (Entry<String,Pair<String,EnumSet<IOStandard>>> e : seriesMacroExpandExceptionMap.entrySet()) {
@@ -1614,44 +1615,29 @@ public void expandMacroUnisims(Series series) {
                         if (!isHDILib) {
                             Pair<String, EnumSet<IOStandard>> exception = seriesMacroExpandExceptionMap.get(cellName);
                             if (exception != null) {
-                                Boolean expand = null;
-                                for (EDIFPropertyValue value : getIOStandards(inst)) {
-                                    IOStandard ioStandard = IOStandard.valueOf(value.getValue());
-                                    boolean contained = exception.getSecond().contains(ioStandard);
-                                    if (expand == null) {
-                                        expand = contained;
-                                    } else {
-                                        if (expand != contained) {
-                                            throw new RuntimeException("ERROR: EDIFCellInst '" + inst + "' has conflicting IOSTANDARDs " +
-                                                    "propagated from multiple top-level nets. Consider uniquifying the EDIFNetlist to " +
-                                                    "enable correct macro expansion.");
-                                        }
-                                    }
-                                }
-                                if (expand) {
+                                if (checkIOStandardForExpansion(inst, exception)) {
                                     cellName = exception.getFirst();
                                 }
                             }
                         }
-                        EDIFCell newCell = netlistPrims.getCell(cellName);
-                        if (newCell == null) {
-                            EDIFCell macro = macros.getCell(cellName);
-                            if (macro == null) {
-                                throw new RuntimeException("failed to find cell macro "+cellName+", we are in "+lib.getName());
-                            }
-                            primsToRemoveOnCollapse.add(cellName);
-                            newCell = new EDIFCell(netlistPrims, macro, cellName);
-                            for (EDIFCellInst childInst : newCell.getCellInsts()) {
-                                EDIFCell primCell = netlistPrims.getCell(childInst.getCellType().getName());
-                                if (primCell == null) {
-                                    primCell = new EDIFCell(netlistPrims, childInst.getCellType());
-                                    primsToRemoveOnCollapse.add(childInst.getCellType().getName());
+                        expandMacroCellType(cellName, inst, macros, netlistPrims);
+                        // Check for multi-level expansion for IOBUFDSE3 (only one known)
+                        if (inst.getCellType().getName().equals("IOBUFDSE3")) {
+                            EDIFCellInst child = inst.getCellType().getCellInst("OBUFTDS");
+                            if (child != null && child.getCellType().getName().equals("OBUFTDS_DCIEN")) {
+                                Pair<String, EnumSet<IOStandard>> exception = seriesMacroExpandExceptionMap
+                                        .get(child.getCellType().getName());
+                                String newChildType = null;
+                                if (exception != null) {
+                                    if (checkIOStandardForExpansion(child, exception)) {
+                                        newChildType = exception.getFirst();
+                                    }
+                                }
+                                if (newChildType != null) {
+                                    expandMacroCellType(newChildType, child, macros, netlistPrims);
                                 }
-                                childInst.setCellType(primCell);
                             }
                         }
-                        assert(newCell == netlistPrims.getCell(cellName));
-                        inst.setCellType(newCell);
                     }
                 }
             }
@@ -1666,6 +1652,48 @@ public void expandMacroUnisims(Series series) {
         }
     }
 
+    private Boolean checkIOStandardForExpansion(EDIFCellInst inst, Pair<String, EnumSet<IOStandard>> exception) {
+        Boolean expand = null;
+        for (EDIFPropertyValue value : getIOStandards(inst)) {
+            IOStandard ioStandard = IOStandard.valueOf(value.getValue());
+            boolean contained = exception.getSecond().contains(ioStandard);
+            if (expand == null) {
+                expand = contained;
+            } else {
+                if (expand != contained) {
+                    throw new RuntimeException("ERROR: EDIFCellInst '" + inst + "' has conflicting IOSTANDARDs "
+                            + "propagated from multiple top-level nets. Consider uniquifying the EDIFNetlist to "
+                            + "enable correct macro expansion.");
+                }
+            }
+        }
+        return expand;
+    }
+
+    private void expandMacroCellType(String newCellType, EDIFCellInst instToExpand, EDIFLibrary macros,
+            EDIFLibrary netlistPrims) {
+        EDIFCell newCell = netlistPrims.getCell(newCellType);
+        if (newCell == null) {
+            EDIFCell macro = macros.getCell(newCellType);
+            if (macro == null) {
+                throw new RuntimeException("failed to find cell macro " + newCellType + ", we are in "
+                        + instToExpand.getParentCell().getLibrary().getName());
+            }
+            primsToRemoveOnCollapse.add(newCellType);
+            newCell = new EDIFCell(netlistPrims, macro, newCellType);
+            for (EDIFCellInst childInst : newCell.getCellInsts()) {
+                EDIFCell primCell = netlistPrims.getCell(childInst.getCellType().getName());
+                if (primCell == null) {
+                    primCell = new EDIFCell(netlistPrims, childInst.getCellType());
+                    primsToRemoveOnCollapse.add(childInst.getCellType().getName());
+                }
+                childInst.setCellType(primCell);
+            }
+        }
+        assert (newCell == netlistPrims.getCell(newCellType));
+        instToExpand.setCellType(newCell);
+    }
+
     /**
      * Collapses any macro primitives back into their primitive state.
      * Performs the opposite of {@link EDIFNetlist#expandMacroUnisims(Series)}.

diff --git a/src/com/xilinx/rapidwright/edif/EDIFPortCache.java b/src/com/xilinx/rapidwright/edif/EDIFPortCache.java
@@ -28,7 +28,7 @@
 import java.util.Map;
 
 /**
- * Cache for speeding up {@link EDIFCell#getPortByLegalName(String)} when querying many ports
+ * Cache for speeding up {@link EDIFCell#getPortByLegalName(String, EDIFReadLegalNameCache)} when querying many ports
  */
 public class EDIFPortCache {
     private final Map<String, EDIFPort> cache;

diff --git a/src/com/xilinx/rapidwright/interchange/DcpToInterchange.java b/src/com/xilinx/rapidwright/interchange/DcpToInterchange.java
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2023, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Author: Zak Nafziger, Advanced Micro Devices, Inc.
+ *
+ * This file is part of RapidWright.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+package com.xilinx.rapidwright.interchange;
+
+import java.io.FileOutputStream;
+import java.io.IOException;
+import java.nio.file.Path;
+import java.nio.file.Paths;
+import java.util.List;
+
+import com.xilinx.rapidwright.design.ConstraintGroup;
+import com.xilinx.rapidwright.design.Design;
+import com.xilinx.rapidwright.ipi.XDCParser;
+import com.xilinx.rapidwright.util.FileTools;
+
+public class DcpToInterchange {
+    public static void main(String[] args) throws IOException {
+        if (args.length != 1) {
+            System.out.println("USAGE: <input.dcp>");
+            return;
+        }
+
+        Design design = Design.readCheckpoint(args[0]);
+        String baseName = Paths.get(args[0]).getFileName().toString();
+        baseName = FileTools.removeFileExtension(baseName);
+        String logNetlistName = baseName + ".netlist";
+        String physNetlistName = baseName + ".phys";
+        String xdcName = baseName + ".xdc";
+
+        LogNetlistWriter.writeLogNetlist(design.getNetlist(), logNetlistName);
+        PhysNetlistWriter.writePhysNetlist(design, physNetlistName);
+
+        List<String> constraints = design.getXDCConstraints(ConstraintGroup.NORMAL);
+        try (FileOutputStream f = new FileOutputStream(xdcName)) {
+            XDCParser.writeXDC(constraints, f);
+        }
+    }
+}
diff --git a/src/com/xilinx/rapidwright/interchange/LogNetlistReader.java b/src/com/xilinx/rapidwright/interchange/LogNetlistReader.java
@@ -138,7 +138,7 @@ protected EDIFCellInst getInst(int i) {
     /**
      * Extracts the property map information from a Cap'n Proto reader object and deserializes it
      * into an EDIF property map object. The reverse function is
-     * {@link LogNetlistWriter#populatePropertyMap(Supplier<PropertyMap.Builder>, EDIFPropertyObject)}
+     * {@link LogNetlistWriter#populatePropertyMap(Supplier, EDIFPropertyObject)}
      * @param reader The Cap'n Proto reader object
      * @param obj The EDIF map object
      */

diff --git a/src/com/xilinx/rapidwright/interchange/PhysNetlistReader.java b/src/com/xilinx/rapidwright/interchange/PhysNetlistReader.java
@@ -344,6 +344,7 @@ protected void readPlacement(PhysNetlist.Reader physNetlist) {
                         c.setSiteInst(siteInst);
                         siteInst.getCellMap().put(belName, c);
                         c.setRoutethru(true);
+                        c.setType(strings.get(placement.getType()));
                     } else {
                         throw new RuntimeException("ERROR: Missing BEL location in other BEL list: "
                                 + belName + " on for pin mapping "

diff --git a/src/com/xilinx/rapidwright/interchange/PhysNetlistWriter.java b/src/com/xilinx/rapidwright/interchange/PhysNetlistWriter.java
@@ -84,9 +84,9 @@ public class PhysNetlistWriter {
     /**
      * The Interchange format allows for all physical routing resources to be
      * specified, e.g.
-     *   ... -> PIP -> SitePin -> BELPin(output) -> BELPin(input) -> SitePIP -> BELPin(output) -> BELPin(input)
+     *   {@code ... -> PIP -> SitePin -> BELPin(output) -> BELPin(input) -> SitePIP -> BELPin(output) -> BELPin(input)}
      * It may not be necessary to use specify all such resources, as many are implied:
-     *   ... -> PIP -> SitePin -> (implied)      -> (implied)     -> SitePIP -> (implied)      -> (implied)
+     *   {@code ... -> PIP -> SitePin -> (implied)      -> (implied)     -> SitePIP -> (implied)      -> (implied)}
      * Disabling this flag allows such implied resources to be omitted.
      */
     public static boolean VERBOSE_PHYSICAL_NET_ROUTING = true;