UltraScale Incremental Clock Router #540
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Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Unit Test Results 45 files 45 suites 8m 0s ⏱️ Results for commit ecf323a. ♻️ This comment has been updated with latest results. |
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Would it be straightforward to generate a test for this? |
If we have a design that had the need, possibly yes. |
I was more alluding to -- do you recall what testcase you used to build this feature? I have a bigger (and the original non-public) testcase that drove this work, but is it straightforward to manufacture a public, clock-specific testcase? |
…_routing Signed-off-by: Chris Lavin <[email protected]>
…_routing Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
Signed-off-by: Chris Lavin <[email protected]>
The only existing DCP in test/RapidWrightDCP that comes close is the microblaze design, but it targets UltraScale. Because it is missing the leaf clock buffers, this code doesn't work for that design scenario. I would have to retarget it to UltraScale+. |
Conflicts: src/com/xilinx/rapidwright/router/UltraScaleClockRouting.java src/com/xilinx/rapidwright/rwroute/GlobalSignalRouting.java
Signed-off-by: Eddie Hung <[email protected]>
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Add a test case for incremental clock routing on UltraScale+. |
* Incremental clock router fixes Signed-off-by: Eddie Hung <[email protected]> * GlobalSignalRouting.routeStaticNet() to not clobber existing PIPs Signed-off-by: Eddie Hung <[email protected]> * Remove redundant PartialRouter.routeStaticNets() override Signed-off-by: Eddie Hung <[email protected]> * Remove import Signed-off-by: Eddie Hung <[email protected]> * Cleanup/document/refactor Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() (#703) * Add test for #701 Signed-off-by: Eddie Hung <[email protected]> * Update testcase and test Signed-off-by: Eddie Hung <[email protected]> * Add testMakePhysNetNamesConsistentLogicalVccGnd() Signed-off-by: Eddie Hung <[email protected]> * Fix DesignTools.makePhysNetNamesConsistent() By transforming logical static nets <const{0,1}> into physical static nets GLOBAL_LOGIC{0,1} Signed-off-by: Eddie Hung <[email protected]> * Update test/src/com/xilinx/rapidwright/design/TestDesignTools.java Signed-off-by: eddieh-xlnx <[email protected]> * Improve testcase, check against Vivado only if present Signed-off-by: Eddie Hung <[email protected]> * Update RapidWrightDCP Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]> * Tidy up Signed-off-by: Eddie Hung <[email protected]> --------- Signed-off-by: Eddie Hung <[email protected]> Signed-off-by: eddieh-xlnx <[email protected]>
Assumes the horizontal distribution lines are already in place, a common technique in DFX designs.