Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

riscv64: Implement insertlane #6408

Merged
merged 9 commits into from
May 20, 2023
Merged

riscv64: Implement insertlane #6408

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
9 commits
Select commit Hold shift + click to select a range
e1eb293
riscv64: Support vector instruction masking
afonso360 May 12, 2023
a4afb9a
riscv64: Add `vmerge` instructions
afonso360 May 12, 2023
d5358b0
riscv64: Implement `insertlane`
afonso360 May 12, 2023
b513fdf
riscv64: Fix encoding of `vmv` instructions
afonso360 May 18, 2023
1f3cafd
riscv64: Fix formatting of mask register
afonso360 May 18, 2023
cd1d8e9
riscv64: Restrict `insertlane` to vector types that fit in a single r…
afonso360 May 18, 2023
0f2909a
wasmtime: Enable more RISC-V SIMD tests
afonso360 May 18, 2023
1e40013
riscv64: Use inline format syntax for printing vector instructions
afonso360 May 20, 2023
a5952ba
riscv64: Add vector mask note
afonso360 May 20, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 0 additions & 5 deletions build.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -210,7 +210,6 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
"issue4807",
"issue_3327_bnot_lowering",
"load_splat_out_of_bounds",
"replace_lane_preserve",
"simd_align",
"simd_bit_shift",
"simd_bitwise",
Expand Down Expand Up @@ -246,10 +245,6 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
"simd_int_to_int_extend",
"simd_lane",
"simd_load",
"simd_load16_lane",
"simd_load32_lane",
"simd_load64_lane",
"simd_load8_lane",
"simd_load_extend",
"simd_load_zero",
"simd_splat",
Expand Down
6 changes: 6 additions & 0 deletions cranelift/codegen/src/isa/riscv64/inst.isle
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -328,25 +328,29 @@
(vd WritableReg)
(vs2 Reg)
(vs1 Reg)
(mask VecOpMasking)
(vstate VState))

(VecAluRRImm5
(op VecAluOpRRImm5)
(vd WritableReg)
(vs2 Reg)
(imm Imm5)
(mask VecOpMasking)
(vstate VState))

(VecAluRR
(op VecAluOpRR)
(vd WritableReg)
(vs Reg)
(mask VecOpMasking)
(vstate VState))

(VecAluRImm5
(op VecAluOpRImm5)
(vd WritableReg)
(imm Imm5)
(mask VecOpMasking)
(vstate VState))

(VecSetState
Expand All @@ -358,13 +362,15 @@
(to WritableReg)
(from VecAMode)
(flags MemFlags)
(mask VecOpMasking)
(vstate VState))

(VecStore
(eew VecElementWidth)
(to VecAMode)
(from Reg)
(flags MemFlags)
(mask VecOpMasking)
(vstate VState))
))

Expand Down
53 changes: 40 additions & 13 deletions cranelift/codegen/src/isa/riscv64/inst/emit.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,6 @@ use crate::ir::RelSourceLoc;
use crate::ir::TrapCode;
use crate::isa::riscv64::inst::*;
use crate::isa::riscv64::inst::{zero_reg, AluOPRRR};
use crate::isa::riscv64::lower::isle::generated_code::VecOpMasking;
use crate::machinst::{AllocationConsumer, Reg, Writable};
use cranelift_control::ControlPlane;
use regalloc2::Allocation;
Expand Down Expand Up @@ -2804,32 +2803,58 @@ impl MachInstEmit for Inst {
sink.bind_label(label_done, &mut state.ctrl_plane);
}
&Inst::VecAluRRR {
op, vd, vs1, vs2, ..
op,
vd,
vs1,
vs2,
ref mask,
..
} => {
let vs1 = allocs.next(vs1);
let vs2 = allocs.next(vs2);
let vd = allocs.next_writable(vd);
let mask = mask.with_allocs(&mut allocs);

sink.put4(encode_valu(op, vd, vs1, vs2, VecOpMasking::Disabled));
sink.put4(encode_valu(op, vd, vs1, vs2, mask));
}
&Inst::VecAluRRImm5 {
op, vd, imm, vs2, ..
op,
vd,
imm,
vs2,
ref mask,
..
} => {
let vs2 = allocs.next(vs2);
let vd = allocs.next_writable(vd);
let mask = mask.with_allocs(&mut allocs);

sink.put4(encode_valu_imm(op, vd, imm, vs2, VecOpMasking::Disabled));
sink.put4(encode_valu_imm(op, vd, imm, vs2, mask));
}
&Inst::VecAluRR { op, vd, vs, .. } => {
&Inst::VecAluRR {
op,
vd,
vs,
ref mask,
..
} => {
let vs = allocs.next(vs);
let vd = allocs.next_writable(vd);
let mask = mask.with_allocs(&mut allocs);

sink.put4(encode_valu_rr(op, vd, vs, VecOpMasking::Disabled));
sink.put4(encode_valu_rr(op, vd, vs, mask));
}
&Inst::VecAluRImm5 { op, vd, imm, .. } => {
&Inst::VecAluRImm5 {
op,
vd,
imm,
ref mask,
..
} => {
let vd = allocs.next_writable(vd);
let mask = mask.with_allocs(&mut allocs);

sink.put4(encode_valu_r_imm(op, vd, imm, VecOpMasking::Disabled));
sink.put4(encode_valu_r_imm(op, vd, imm, mask));
}
&Inst::VecSetState { rd, ref vstate } => {
let rd = allocs.next_writable(rd);
Expand All @@ -2849,11 +2874,13 @@ impl MachInstEmit for Inst {
eew,
to,
ref from,
ref mask,
flags,
..
} => {
let from = from.clone().with_allocs(&mut allocs);
let to = allocs.next_writable(to);
let mask = mask.with_allocs(&mut allocs);

// Vector Loads don't support immediate offsets, so we need to load it into a register.
let addr = match from {
Expand Down Expand Up @@ -2889,8 +2916,7 @@ impl MachInstEmit for Inst {
eew,
addr,
from.lumop(),
// We don't implement masking yet.
VecOpMasking::Disabled,
mask,
from.mop(),
from.nf(),
));
Expand All @@ -2900,11 +2926,13 @@ impl MachInstEmit for Inst {
eew,
ref to,
from,
ref mask,
flags,
..
} => {
let to = to.clone().with_allocs(&mut allocs);
let from = allocs.next(from);
let mask = mask.with_allocs(&mut allocs);

// Vector Stores don't support immediate offsets, so we need to load it into a register.
let addr = match to {
Expand Down Expand Up @@ -2940,8 +2968,7 @@ impl MachInstEmit for Inst {
eew,
addr,
to.sumop(),
// We don't implement masking yet.
VecOpMasking::Disabled,
mask,
to.mop(),
to.nf(),
));
Expand Down
Loading