Remove TransitName and code used only by it

core/src/main/scala/chisel3/internal/Builder.scala

@@ -109,12 +109,6 @@ private[chisel3] trait HasId extends InstanceId {
   // - Overridden when [[suggestSeed]] or [[autoSeed]] is called
   private var naming_prefix: Prefix = Builder.getPrefix
 
-  // Post-seed hooks called to carry the suggested seeds to other candidates as needed
-  private var suggest_postseed_hooks: List[String => Unit] = Nil
-
-  // Post-seed hooks called to carry the auto seeds to other candidates as needed
-  private var auto_postseed_hooks: List[String => Unit] = Nil
-
   /** Takes the last seed suggested. Multiple calls to this function will take the last given seed, unless
     * this HasId is a module port (see overridden method in Data.scala).
     *
@@ -131,7 +125,6 @@ private[chisel3] trait HasId extends InstanceId {
   // Bypass the overridden behavior of autoSeed in [[Data]], apply autoSeed even to ports
   private[chisel3] def forceAutoSeed(seed: String): this.type = {
     auto_seed = Some(seed)
-    for (hook <- auto_postseed_hooks.reverse) { hook(seed) }
     naming_prefix = Builder.getPrefix
     this
   }
@@ -160,7 +153,6 @@ private[chisel3] trait HasId extends InstanceId {
   def suggestName(seed: => String): this.type = {
     if (suggested_seed.isEmpty) suggested_seed = Some(seed)
     naming_prefix = Builder.getPrefix
-    for (hook <- suggest_postseed_hooks.reverse) { hook(seed) }
     this
   }
 
@@ -196,9 +188,6 @@ private[chisel3] trait HasId extends InstanceId {
 
   private[chisel3] def hasAutoSeed: Boolean = auto_seed.isDefined
 
-  private[chisel3] def addSuggestPostnameHook(hook: String => Unit): Unit = suggest_postseed_hooks ::= hook
-  private[chisel3] def addAutoPostnameHook(hook:    String => Unit): Unit = auto_postseed_hooks ::= hook
-
   // Uses a namespace to convert suggestion into a true name
   // Will not do any naming if the reference already assigned.
   // (e.g. tried to suggest a name to part of a Record)

src/main/scala/chisel3/util/Decoupled.scala

@@ -366,7 +366,7 @@ object Queue {
       q.io.enq.valid := enq.valid // not using <> so that override is allowed
       q.io.enq.bits := enq.bits
       enq.ready := q.io.enq.ready
-      TransitName(q.io.deq, q)
+      q.io.deq
     }
   }
 

src/main/scala/chisel3/util/Valid.scala

@@ -6,6 +6,7 @@
 package chisel3.util
 
 import chisel3._
+import chisel3.experimental.prefix
 
 import scala.annotation.nowarn
 
@@ -15,7 +16,7 @@ import scala.annotation.nowarn
   * to put back pressure on the producer.
   *
   * In most scenarios, the `Valid` class will ''not'' be used directly. Instead, users will create `Valid` interfaces
-  * using the [[Valid$ Valid factory]]sbt.
+  * using the [[Valid$ Valid factory]].
   * @tparam T the type of the data
   * @param gen some data
   * @see [[Valid$ Valid factory]] for concrete examples
@@ -126,14 +127,12 @@ object Pipe {
       out.valid := enqValid
       out.bits := enqBits
       out
-    } else {
-      val v = RegNext(enqValid, false.B)
-      val b = RegEnable(enqBits, enqValid)
-      val out = apply(v, b, latency - 1)(compileOptions)
-
-      TransitName.withSuffix("Pipe_valid")(out, v)
-      TransitName.withSuffix("Pipe_bits")(out, b)
-    }
+    } else
+      prefix("pipe") {
+        val v = RegNext(enqValid, false.B)
+        val b = RegEnable(enqBits, enqValid)
+        apply(v, b, latency - 1)(compileOptions)
+      }
   }
 
   /** Generate a one-stage pipe from an explicit valid bit and some data

src/test/scala/chiselTests/QueueSpec.scala

@@ -9,6 +9,8 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 import chisel3.util.random.LFSR
 
+import chisel3.stage.ChiselStage
+
 class ThingsPassThroughTester(
   elements:       Seq[Int],
   queueDepth:     Int,
@@ -291,4 +293,19 @@ class QueueSpec extends ChiselPropSpec {
     (new chisel3.stage.phases.Elaborate)
       .transform(Seq(chisel3.stage.ChiselGeneratorAnnotation(() => new IrrevocableQueue)))
   }
+
+  property("Queue.apply should have decent names") {
+    class HasTwoQueues extends Module {
+      val in = IO(Flipped(Decoupled(UInt(8.W))))
+      val out = IO(Decoupled(UInt(8.W)))
+
+      val foo = Queue(in, 2)
+      val bar = Queue(foo, 2)
+      out <> bar
+    }
+
+    val chirrtl = ChiselStage.emitChirrtl(new HasTwoQueues)
+    chirrtl should include("inst foo_q of Queue")
+    chirrtl should include("inst bar_q of Queue")
+  }
 }

src/test/scala/chiselTests/util/PipeSpec.scala

@@ -0,0 +1,40 @@
+package chiselTests.util
+
+// SPDX-License-Identifier: Apache-2.0
+
+import chisel3._
+import chisel3.util.{Pipe, Valid}
+import chisel3.stage.ChiselStage.emitChirrtl
+import chisel3.experimental.FlatIO
+import chiselTests.ChiselFlatSpec
+
+class PipeSpec extends ChiselFlatSpec {
+  behavior.of("Pipe")
+
+  it should "Have decent names for Pipe(2)" in {
+    class MyModule extends Module {
+      val foo = IO(Input(Valid(UInt(8.W))))
+      val bar = IO(Output(Valid(UInt(8.W))))
+      bar := Pipe(foo.valid, bar.bits, 2)
+    }
+    val chirrtl = emitChirrtl(new MyModule)
+    chirrtl should include("reg bar_pipe_v")
+    chirrtl should include("reg bar_pipe_pipe_v")
+    chirrtl should include("wire bar_pipe_pipe_out")
+    chirrtl should include("bar_pipe_pipe_out.valid <= bar_pipe_pipe_v")
+    chirrtl should include("bar <= bar_pipe_pipe_out")
+  }
+
+  it should "Have decent names for Pipe(0)" in {
+    class MyModule extends Module {
+      val foo = IO(Input(Valid(UInt(8.W))))
+      val bar = IO(Output(Valid(UInt(8.W))))
+      bar := Pipe(foo.valid, foo.bits, 0)
+    }
+    val chirrtl = emitChirrtl(new MyModule)
+    (chirrtl should not).include("pipe")
+    chirrtl should include("wire bar_out")
+    chirrtl should include("bar_out.valid <= foo.valid")
+    chirrtl should include("bar <= bar_out")
+  }
+}