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Issues: forsyde/forsyde-deep
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multidimentional fixed size vector error in modelsim simulation on generated vhdl code
#41
opened Oct 22, 2022 by
fuzhouxiang
VHDL backend support for arbitrary function orders in where clauses
enhancement
#20
opened Mar 24, 2016 by
HWoidt
VHDL Backend: Range mismatch between Haskell's Int32 and Minimum VHDL'93 Integer range
question
#17
opened Mar 24, 2016 by
HWoidt
Improve support for Case expressions in the VHDL backend
enhancement
#15
opened Mar 24, 2016 by
HWoidt
Compile forsyde.vhd on demand instead of during compilation
enhancement
entry level
#9
opened Mar 24, 2016 by
HWoidt
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