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[RISCV][GlobalISel] Select G_FRAME_INDEX #68254

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merged 6 commits into from
Oct 18, 2023
Merged

[RISCV][GlobalISel] Select G_FRAME_INDEX #68254

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7a21ee3
[RISCV][GlobalISel] Select G_FRAME_INDEX
nitinjohnraj Oct 3, 2023
5d058ee
Made comment clearer
nitinjohnraj Oct 4, 2023
6bae77c
Remove unnecessary pointer check
nitinjohnraj Oct 6, 2023
26976eb
Remove unused DstReg
nitinjohnraj Oct 6, 2023
48a4ba4
Merge branch 'main' into sel-frame-index
nitinjohnraj Oct 6, 2023
2de47e3
Add test for frame index register bank selection
nitinjohnraj Oct 10, 2023
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8 changes: 8 additions & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -245,6 +245,14 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
}
case TargetOpcode::G_SEXT_INREG:
return selectSExtInreg(MI, MIB);
case TargetOpcode::G_FRAME_INDEX: {
// TODO: We may want to replace this code with the SelectionDAG patterns,
// which fail to get imported because it uses FrameAddrRegImm, which is a
// ComplexPattern
MI.setDesc(TII.get(RISCV::ADDI));
MI.addOperand(MachineOperand::CreateImm(0));
return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
}
case TargetOpcode::G_SELECT:
return selectSelect(MI, MIB, MRI);
default:
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1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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Expand Up @@ -127,6 +127,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case TargetOpcode::G_STORE:
break;
case TargetOpcode::G_CONSTANT:
case TargetOpcode::G_FRAME_INDEX:
case TargetOpcode::G_GLOBAL_VALUE:
case TargetOpcode::G_BRCOND:
OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
Expand Down
32 changes: 32 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
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@@ -0,0 +1,32 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
--- |
define ptr @frame_index() {
entry:
%x = alloca i32, align 4
ret ptr %x
}

...
---
name: frame_index
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gprb, preferred-register: '' }
stack:
- { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
bb.1.entry:
; CHECK-LABEL: name: frame_index
; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
; CHECK-NEXT: $x10 = COPY [[ADDI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(p0) = G_FRAME_INDEX %stack.0.x
$x10 = COPY %0(p0)
PseudoRET implicit $x10

...
32 changes: 32 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
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@@ -0,0 +1,32 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
--- |
define ptr @frame_index() {
entry:
%x = alloca i32, align 4
ret ptr %x
}

...
---
name: frame_index
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gprb, preferred-register: '' }
stack:
- { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
bb.1.entry:
; CHECK-LABEL: name: frame_index
; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
; CHECK-NEXT: $x10 = COPY [[ADDI]]
; CHECK-NEXT: PseudoRET implicit $x10
%0:gprb(p0) = G_FRAME_INDEX %stack.0.x
$x10 = COPY %0(p0)
PseudoRET implicit $x10

...
33 changes: 33 additions & 0 deletions llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/frame-index.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -run-pass=regbankselect %s -o - \
# RUN: | FileCheck %s
# RUN: llc -mtriple=riscv64 -run-pass=regbankselect %s -o - \
# RUN: | FileCheck %s
--- |
define ptr @frame_index() {
entry:
%x = alloca i32, align 4
ret ptr %x
}

...
---
name: frame_index
legalized: true
registers:
- { id: 0, class: _, preferred-register: '' }
stack:
- { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
bb.1.entry:
; CHECK-LABEL: name: frame_index
; CHECK: [[FRAME_INDEX:%[0-9]+]]:gprb(p0) = G_FRAME_INDEX %stack.0.x
; CHECK-NEXT: $x10 = COPY [[FRAME_INDEX]](p0)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(p0) = G_FRAME_INDEX %stack.0.x
$x10 = COPY %0(p0)
PseudoRET implicit $x10

...