[RISCV][GlobalISel] Select G_FRAME_INDEX

[nitinjohnraj]

This patch is a bandage to get G_FRAME_INDEX working. We could import the SelectionDAG patterns for the ComplexPattern FrameAddrRegImm, and perhaps we will do that in the future. For now we just select it as an addition with 0.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v

@llvm/pr-subscribers-llvm-globalisel

Changes

This patch is a bandage to get G_FRAME_INDEX working. We could import the SelectionDAG patterns for the ComplexPattern FrameAddrRegImm, and perhaps we will do that in the future. For now we just select it as an addition with 0.

---

Full diff: https://github.com/llvm/llvm-project/pull/68254.diff

5 Files Affected:

• (modified) llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp (+10)
• (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+2)
• (modified) llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp (+1)
• (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir (+32)
• (added) llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir (+32)

diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 4f97a0d84f686f9..99bcaf7d7977c49 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -239,6 +239,16 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   }
   case TargetOpcode::G_SEXT_INREG:
     return selectSExtInreg(MI, MIB);
+  case TargetOpcode::G_FRAME_INDEX: {
+    Register DstReg = MI.getOperand(0).getReg();
+
+    if (!MRI.getType(DstReg).isPointer())
+      return false;
+
+    MI.setDesc(TII.get(RISCV::ADDI));
+    MI.addOperand(MachineOperand::CreateImm(0));
+    return constrainSelectedInstRegOperands(MI, TII, TRI, RBI);
+  }
   default:
     return false;
   }
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index f12e868e74264f6..4479bccfd45e396 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -169,6 +169,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
 
   getActionDefinitionsBuilder(G_ABS).lower();
 
+  getActionDefinitionsBuilder(G_FRAME_INDEX).legalFor({p0});
+
   getLegacyLegalizerInfo().computeTables();
 }
 
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index 63686bd4bdbc3ae..59aebc7960bc3dc 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -127,6 +127,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_STORE:
     break;
   case TargetOpcode::G_CONSTANT:
+  case TargetOpcode::G_FRAME_INDEX:
   case TargetOpcode::G_GLOBAL_VALUE:
   case TargetOpcode::G_BRCOND:
     OperandsMapping = getOperandsMapping({GPRValueMapping, nullptr});
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
new file mode 100644
index 000000000000000..20747bd1876180c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv32.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+  define ptr @frame_index() {
+  entry:
+    %x = alloca i32, align 4
+    ret ptr %x
+  }
+
+...
+---
+name:            frame_index
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gprb, preferred-register: '' }
+stack:
+  - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: frame_index
+    ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
new file mode 100644
index 000000000000000..dc265bda0a68894
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/frame-index-rv64.mir
@@ -0,0 +1,32 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
+# RUN: | FileCheck %s
+--- |
+  define ptr @frame_index() {
+  entry:
+    %x = alloca i32, align 4
+    ret ptr %x
+  }
+
+...
+---
+name:            frame_index
+legalized:       true
+regBankSelected: true
+registers:
+  - { id: 0, class: gprb, preferred-register: '' }
+stack:
+  - { id: 0, name: x, type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: frame_index
+    ; CHECK: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.x, 0
+    ; CHECK-NEXT: $x10 = COPY [[ADDI]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %0:gprb(p0) = G_FRAME_INDEX %stack.0.x
+    $x10 = COPY %0(p0)
+    PseudoRET implicit $x10
+
+...

[mshockwave]

LGTM. Please consider pushing new commit instead of forced push (unless it's to rebase on critical fixes) though.

[topperc]

Missing test for register bank selection

[topperc]

LGTM