[RACL] Create a unified error log output, error arbitration, and more

[Razer6]

This PR improves and fixes multiple issues with RACL:

1. It merges the previous error and error log output. In particular, it adds the error status signal in the form of a valid bit to the error log struct. This change is passed through all RACL consumers and the tops are re-generated.
2. The policy vector is assigned in the opposite order. Policy 0 is rendered first, which is the last element of the assign vector.
3. The default policy values are rendered as parameters, which are completely unused - remove them.
4. It separates the top-sepcific policy selection vectors from top_racl_pkg.sv into a top-specific top_<topname>_racl_pkg.sv. This file must be added per top, wich would not be possible if it is rendered in its top_racl_pkg.sv.
5. Arbitrate between multiple incoming errors in racl_ctrl.

[alees24]

Thanks. This looks fine to me; just one question really about the arbitration but if that change is made I'm happy for it to be deferred.

[andreaskurth]

LGTM, thx @Razer6!

[andreaskurth]

Each top still has top_racl_pkg because that allows IPs to reference RACL symbols in SV code without having to be IPgen'd, right?

[Razer6]

Exactly. That one carries the generic information that one IP needs, such as the struct definitions. There is one provider of the virtual core top_racl_pkg in the top. That one is also use across multiple tops in a design (if used). When multiple tops come into play, each top needs to place its own unique definition into a uniquified package top_<top_name>_racl_pkg. These can exist multiple times for multiple tops because of uniquification.

[andreaskurth]

@Razer6: If you could rebase this PR and it passes CI, we should be able to merge this

[alees24]

@Razer6: If you could rebase this PR and it passes CI, we should be able to merge this
Agreed. I locally rebased on top of the Darjeeling DV PR and ran chip_sw_uart_smoketest successfully.

[Razer6]

@Razer6: If you could rebase this PR and it passes CI, we should be able to merge this

Yeah, I still need to think about a solution that now occurs with rebasing and in combination with this PR. So with this PR, we now arbitrate between different, possibly simultaneous, occurring incoming errors in racl_ctrl.

This problem also arise now within the sram_ctrl IP itself, or any other IP that uses multiple RACL checks in parallel. In sram_ctrl, a RACL check happens in the reg_top and in the sram adapter. Those might occur in parallel, for example there are still outstanding transfers that target sran_ctrl's RAM + one register access.

What we would need to do here is to arbitrate between all error sources inside and IP and return one error log. In case of more than one error, the error struct needs to include and overflow bit, that is routed to racl_ctrl's overflow bit.

@alees24 @andreaskurth What do you think about that?

[alees24]

@Razer6: If you could rebase this PR and it passes CI, we should be able to merge this

Yeah, I still need to think about a solution that now occurs with rebasing and in combination with this PR. So with this PR, we now arbitrate between different, possibly simultaneous, occurring incoming errors in racl_ctrl.

This problem also arise now within the sram_ctrl IP itself, or any other IP that uses multiple RACL checks in parallel. In sram_ctrl, a RACL check happens in the reg_top and in the sram adapter. Those might occur in parallel, for example there are still outstanding transfers that target sran_ctrl's RAM + one register access.

What we would need to do here is to arbitrate between all error sources inside and IP and return one error log. In case of more than one error, the error struct needs to include and overflow bit, that is routed to racl_ctrl's overflow bit.

@alees24 @andreaskurth What do you think about that?

I suppose the simple solution is simply to track two racl_error_log_t structures from those IP blocks to racl_ctrl but perhaps that's not acceptable, and I guess it doesn't scale very well.

The alternative thought that occurs is perhaps you could move the prim_arbiter_fixed and immediately-surrounding logic into a parameterized submodule that receives a N racl_error_log_t structures and produces one at its output, with the racl_error_log_t structure widened to include an overflow bit as you describe. The output 'overflow' bit would of course be the OR of all input 'overflows' and any newly-generated overflow.

Let us suppose that the naming is racl_error_m1 mirroring the naming convention in the tlul_socket_m1, that then gets instantiated at the device end and in racl_ctrl:

 - sram_ctrl
   - u_racl_error_m1, M = 2
- racl_ctrl
  -  u_racl_error_m1, M = NumAllIps

That's the more general solution, which does mean more churn, but perhaps it would be better to accept that at this stage, as part of this PR.

I'd be happy enough with that, and it may actually provide a means of resolving any timing issues that result from the RACL wiring spanning the entire design, if an optional register stage delay can be introduced with a parameter.

[Razer6]

The alternative thought that occurs is perhaps you could move the prim_arbiter_fixed and immediately-surrounding logic into a parameterized submodule that receives a N racl_error_log_t structures and produces one at its output, with the racl_error_log_t structure widened to include an overflow bit as you describe. The output 'overflow' bit would of course be the OR of all input 'overflows' and any newly-generated overflow.

I also didn't want to introduce a non-scaling solution which does not scale very well. I instead went the route to introduce a prim_racl_error_arb that arbitrates between simultaneous errors and computes the overflow bit locally, if there are multiple errors. The same module is used in racl_ctrl, to decide on the error. I think that is the best solution and it also cleans up the code for IP-local arbitration.

[alees24]

CHANGE AUTHORIZED: hw/ip/gpio/data/gpio.hjson
CHANGE AUTHORIZED: hw/ip/gpio/rtl/gpio.sv
CHANGE AUTHORIZED: hw/ip/gpio/rtl/gpio_reg_top.sv
CHANGE AUTHORIZED: hw/ip/i2c/data/i2c.hjson
CHANGE AUTHORIZED: hw/ip/i2c/rtl/i2c.sv
CHANGE AUTHORIZED: hw/ip/i2c/rtl/i2c_reg_top.sv
CHANGE AUTHORIZED: hw/ip/prim/rtl/prim_racl_error_arb.sv
CHANGE AUTHORIZED: hw/ip/pwm/data/pwm.hjson
CHANGE AUTHORIZED: hw/ip/pwm/rtl/pwm.sv
CHANGE AUTHORIZED: hw/ip/pwm/rtl/pwm_reg_top.sv
CHANGE AUTHORIZED: hw/ip/spi_device/data/spi_device.hjson
CHANGE AUTHORIZED: hw/ip/spi_device/rtl/spi_device.sv
CHANGE AUTHORIZED: hw/ip/spi_device/rtl/spi_device_reg_top.sv
CHANGE AUTHORIZED: hw/ip/spi_host/data/spi_host.hjson
CHANGE AUTHORIZED: hw/ip/spi_host/rtl/spi_host.sv
CHANGE AUTHORIZED: hw/ip/spi_host/rtl/spi_host_reg_top.sv
CHANGE AUTHORIZED: hw/ip/spi_host/rtl/spi_host_window.sv
CHANGE AUTHORIZED: hw/ip/sram_ctrl/data/sram_ctrl.hjson
CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl.sv
CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl_ram_reg_top.sv
CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl_regs_reg_top.sv
CHANGE AUTHORIZED: hw/ip/tlul/rtl/tlul_adapter_reg_racl.sv
CHANGE AUTHORIZED: hw/ip/tlul/rtl/tlul_adapter_sram_racl.sv
CHANGE AUTHORIZED: hw/ip/uart/data/uart.hjson
CHANGE AUTHORIZED: hw/ip/uart/rtl/uart.sv
CHANGE AUTHORIZED: hw/ip/uart/rtl/uart_reg_top.sv
CHANGE AUTHORIZED: hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

[alees24]

I ran the top-level uart smoketest with the new arbitration logic without issue. LGTM, thanks.

Just one observation going forwards; as RACL is added into other blocks, could you please add the port connections into the DUT instances in the block-level test benches and do a build test? A missing, unused output port in the instantiation is usually not a problem (except for Verilator test benches) but it's good to keep the instantiations and definitions in step.

[andreaskurth]

CHANGE AUTHORIZED: hw/ip/gpio/data/gpio.hjson
CHANGE AUTHORIZED: hw/ip/gpio/rtl/gpio.sv
CHANGE AUTHORIZED: hw/ip/gpio/rtl/gpio_reg_top.sv
CHANGE AUTHORIZED: hw/ip/i2c/data/i2c.hjson
CHANGE AUTHORIZED: hw/ip/i2c/rtl/i2c.sv
CHANGE AUTHORIZED: hw/ip/i2c/rtl/i2c_reg_top.sv
CHANGE AUTHORIZED: hw/ip/prim/rtl/prim_racl_error_arb.sv
CHANGE AUTHORIZED: hw/ip/pwm/data/pwm.hjson
CHANGE AUTHORIZED: hw/ip/pwm/rtl/pwm.sv
CHANGE AUTHORIZED: hw/ip/pwm/rtl/pwm_reg_top.sv
CHANGE AUTHORIZED: hw/ip/spi_device/data/spi_device.hjson
CHANGE AUTHORIZED: hw/ip/spi_device/rtl/spi_device.sv
CHANGE AUTHORIZED: hw/ip/spi_device/rtl/spi_device_reg_top.sv
CHANGE AUTHORIZED: hw/ip/spi_host/data/spi_host.hjson
CHANGE AUTHORIZED: hw/ip/spi_host/rtl/spi_host.sv
CHANGE AUTHORIZED: hw/ip/spi_host/rtl/spi_host_reg_top.sv
CHANGE AUTHORIZED: hw/ip/spi_host/rtl/spi_host_window.sv
CHANGE AUTHORIZED: hw/ip/sram_ctrl/data/sram_ctrl.hjson
CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl.sv
CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl_ram_reg_top.sv
CHANGE AUTHORIZED: hw/ip/sram_ctrl/rtl/sram_ctrl_regs_reg_top.sv
CHANGE AUTHORIZED: hw/ip/tlul/rtl/tlul_adapter_reg_racl.sv
CHANGE AUTHORIZED: hw/ip/tlul/rtl/tlul_adapter_sram_racl.sv
CHANGE AUTHORIZED: hw/ip/uart/data/uart.hjson
CHANGE AUTHORIZED: hw/ip/uart/rtl/uart.sv
CHANGE AUTHORIZED: hw/ip/uart/rtl/uart_reg_top.sv
CHANGE AUTHORIZED: hw/top_earlgrey/rtl/autogen/top_earlgrey.sv

All these changes are related to RACL, which isn't fully stable yet.