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[RACL] Create a unified error log output, error arbitration, and more #26184

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merged 9 commits into from
Feb 14, 2025
Merged

[RACL] Create a unified error log output, error arbitration, and more #26184

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85df8f6
[racl] Merge racl_error and racl_error_log to a unified struct
Razer6 Feb 10, 2025
60771f7
[top] Re-generate top after RACL interface changes
Razer6 Feb 10, 2025
ece73ab
[hw,racl_ctrl,rtl] Reverse order of policies for assign statement
Razer6 Feb 10, 2025
95de9d2
[hw,racl,rtl] Do not render policy default values -> unneeded
Razer6 Feb 10, 2025
a5412ff
[racl] Uniquify parameter selection vectors to a top-specifiy package
Razer6 Feb 10, 2025
562e204
[hw,racl_ctrl,rtl] Arbitrate multiple incoming errors
Razer6 Feb 10, 2025
f51115f
[racl] Add overflow information to error log
Razer6 Feb 13, 2025
d8fc94a
[racl] Add an error log arbiter primitive
Razer6 Feb 13, 2025
d0be10b
[racl] Arbitrate IP internal simultaneous errors
Razer6 Feb 14, 2025
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12 changes: 1 addition & 11 deletions hw/ip/gpio/data/gpio.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -134,19 +134,9 @@
The policy selection vector (parameter) selects the policy for each register.
'''
}
{ struct: "logic",
type: "uni",
name: "racl_error",
act: "req",
width : "1",
desc: '''
RACL error indication signal.
If 1, the error log contains valid information.
'''
}
{ struct: "racl_error_log",
type: "uni",
name: "racl_error_log",
name: "racl_error",
act: "req",
width: "1"
package: "top_racl_pkg",
Expand Down
3 changes: 1 addition & 2 deletions hw/ip/gpio/doc/interfaces.md
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Expand Up @@ -20,8 +20,7 @@ Referring to the [Comportable guideline for peripheral device functionality](htt
| strap_en | logic | uni | rcv | 1 | This signal is pulsed high by the power manager after reset in order to sample the HW straps. |
| sampled_straps | gpio_pkg::gpio_straps | uni | req | 1 | This vector contains the sampled strap values. |
| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register. |
| racl_error | logic | uni | req | 1 | RACL error indication signal. If 1, the error log contains valid information. |
| racl_error_log | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. |
| racl_error | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |

## Interrupts
Expand Down
7 changes: 2 additions & 5 deletions hw/ip/gpio/rtl/gpio.sv
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Expand Up @@ -38,8 +38,7 @@ module gpio

// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o,
output top_racl_pkg::racl_error_log_t racl_error_o,

// GPIOs
input [31:0] cio_gpio_i,
Expand Down Expand Up @@ -234,7 +233,6 @@ module gpio

.racl_policies_i,
.racl_error_o,
.racl_error_log_o,

// SEC_CM: BUS.INTEGRITY
.intg_err_o (alerts[0])
Expand All @@ -245,8 +243,7 @@ module gpio
`ASSERT_KNOWN(CioGpioEnOKnown, cio_gpio_en_o)
`ASSERT_KNOWN(CioGpioOKnown, cio_gpio_o)
`ASSERT_KNOWN(AlertsKnown_A, alert_tx_o)
`ASSERT_KNOWN(RaclErrorKnown_A, racl_error_o)
`ASSERT_KNOWN(RaclErrorLogKnown_A, racl_error_log_o)
`ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid)

// Alert assertions for reg_we onehot check
`ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0])
Expand Down
20 changes: 10 additions & 10 deletions hw/ip/gpio/rtl/gpio_reg_top.sv
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Expand Up @@ -23,8 +23,7 @@ module gpio_reg_top

// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o,
output top_racl_pkg::racl_error_log_t racl_error_o,

// Integrity check errors
output logic intg_err_o
Expand Down Expand Up @@ -122,7 +121,7 @@ module gpio_reg_top
.busy_i (reg_busy),
.rdata_i (reg_rdata),
// Translate RACL error to TLUL error if enabled
.error_i (reg_error | (RaclErrorRsp & racl_error_o))
.error_i (reg_error | (RaclErrorRsp & racl_error_o.valid))
);

// cdc oversampling signals
Expand Down Expand Up @@ -765,16 +764,17 @@ module gpio_reg_top

assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// A valid address hit, access, but failed the RACL check
assign racl_error_o = |addr_hit & ((reg_re & ~|racl_addr_hit_read) |
(reg_we & ~|racl_addr_hit_write));
assign racl_error_log_o.racl_role = racl_role;
assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) |
(reg_we & ~|racl_addr_hit_write));
assign racl_error_o.racl_role = racl_role;
assign racl_error_o.overflow = 1'b0;

if (EnableRacl) begin : gen_racl_log
assign racl_error_log_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
assign racl_error_log_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
end else begin : gen_no_racl_log
assign racl_error_log_o.ctn_uid = '0;
assign racl_error_log_o.read_access = 1'b0;
assign racl_error_o.ctn_uid = '0;
assign racl_error_o.read_access = 1'b0;
end

// Check sub-word write is permitted
Expand Down
12 changes: 1 addition & 11 deletions hw/ip/i2c/data/i2c.hjson
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Expand Up @@ -140,19 +140,9 @@
The policy selection vector (parameter) selects the policy for each register.
'''
}
{ struct: "logic",
type: "uni",
name: "racl_error",
act: "req",
width : "1",
desc: '''
RACL error indication signal.
If 1, the error log contains valid information.
'''
}
{ struct: "racl_error_log",
type: "uni",
name: "racl_error_log",
name: "racl_error",
act: "req",
width: "1"
package: "top_racl_pkg",
Expand Down
17 changes: 8 additions & 9 deletions hw/ip/i2c/doc/interfaces.md
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Expand Up @@ -16,15 +16,14 @@ Referring to the [Comportable guideline for peripheral device functionality](htt

## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling)

| Port Name | Package::Struct | Type | Act | Width | Description |
|:---------------|:--------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------|
| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_rsp | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | |
| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. |
| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register. |
| racl_error | logic | uni | req | 1 | RACL error indication signal. If 1, the error log contains valid information. |
| racl_error_log | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |
| Port Name | Package::Struct | Type | Act | Width | Description |
|:--------------|:--------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------------------|
| ram_cfg | prim_ram_1p_pkg::ram_1p_cfg | uni | rcv | 1 | |
| ram_cfg_rsp | prim_ram_1p_pkg::ram_1p_cfg_rsp | uni | req | 1 | |
| lsio_trigger | logic | uni | req | 1 | Self-clearing status trigger for the DMA. Set when RX TX FIFO is past their configured watermark matching watermark interrupt behaviour. |
| racl_policies | top_racl_pkg::racl_policy_vec | uni | rcv | 1 | Incoming RACL policy vector from a racl_ctrl instance. The policy selection vector (parameter) selects the policy for each register. |
| racl_error | top_racl_pkg::racl_error_log | uni | req | 1 | RACL error log information of this module. |
| tl | tlul_pkg::tl | req_rsp | rsp | 1 | |

## Interrupts

Expand Down
7 changes: 2 additions & 5 deletions hw/ip/i2c/rtl/i2c.sv
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Expand Up @@ -30,8 +30,7 @@ module i2c

// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o,
output top_racl_pkg::racl_error_log_t racl_error_o,

// Generic IO
input cio_scl_i,
Expand Down Expand Up @@ -79,7 +78,6 @@ module i2c
.hw2reg,
.racl_policies_i,
.racl_error_o,
.racl_error_log_o,
// SEC_CM: BUS.INTEGRITY
.intg_err_o(alerts[0])
);
Expand Down Expand Up @@ -176,8 +174,7 @@ module i2c
`ASSERT_KNOWN(IntrUnexpStopKnownO_A, intr_unexp_stop_o)
`ASSERT_KNOWN(IntrHostTimeoutKnownO_A, intr_host_timeout_o)
`ASSERT_KNOWN(LsioTriggerKnown_A, lsio_trigger_o)
`ASSERT_KNOWN(RaclErrorKnown_A, racl_error_o)
`ASSERT_KNOWN(RaclErrorLogKnown_A, racl_error_log_o)
`ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid)

// Alert assertions for reg_we onehot check
`ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegWeOnehotCheck_A, u_reg, alert_tx_o[0])
Expand Down
20 changes: 10 additions & 10 deletions hw/ip/i2c/rtl/i2c_reg_top.sv
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Expand Up @@ -23,8 +23,7 @@ module i2c_reg_top

// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o,
output top_racl_pkg::racl_error_log_t racl_error_o,

// Integrity check errors
output logic intg_err_o
Expand Down Expand Up @@ -122,7 +121,7 @@ module i2c_reg_top
.busy_i (reg_busy),
.rdata_i (reg_rdata),
// Translate RACL error to TLUL error if enabled
.error_i (reg_error | (RaclErrorRsp & racl_error_o))
.error_i (reg_error | (RaclErrorRsp & racl_error_o.valid))
);

// cdc oversampling signals
Expand Down Expand Up @@ -3473,16 +3472,17 @@ module i2c_reg_top

assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// A valid address hit, access, but failed the RACL check
assign racl_error_o = |addr_hit & ((reg_re & ~|racl_addr_hit_read) |
(reg_we & ~|racl_addr_hit_write));
assign racl_error_log_o.racl_role = racl_role;
assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) |
(reg_we & ~|racl_addr_hit_write));
assign racl_error_o.racl_role = racl_role;
assign racl_error_o.overflow = 1'b0;

if (EnableRacl) begin : gen_racl_log
assign racl_error_log_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
assign racl_error_log_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
end else begin : gen_no_racl_log
assign racl_error_log_o.ctn_uid = '0;
assign racl_error_log_o.read_access = 1'b0;
assign racl_error_o.ctn_uid = '0;
assign racl_error_o.read_access = 1'b0;
end

// Check sub-word write is permitted
Expand Down
12 changes: 1 addition & 11 deletions hw/ip/mbx/data/mbx.hjson
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Expand Up @@ -62,19 +62,9 @@
The policy selection vector (parameter) selects the policy for each register.
'''
}
{ struct: "logic",
type: "uni",
name: "racl_error",
act: "req",
width : "1",
desc: '''
RACL error indication signal.
If 1, the error log contains valid information.
'''
}
{ struct: "racl_error_log",
type: "uni",
name: "racl_error_log",
name: "racl_error",
act: "req",
width: "1"
package: "top_racl_pkg",
Expand Down
1 change: 1 addition & 0 deletions hw/ip/mbx/mbx.core
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Expand Up @@ -8,6 +8,7 @@ filesets:
files_rtl:
depend:
- lowrisc:prim:all
- lowrisc:prim:racl_error_arb
- lowrisc:tlul:headers
- lowrisc:ip:tlul
- lowrisc:systems:top_racl_pkg
Expand Down
9 changes: 3 additions & 6 deletions hw/ip/mbx/rtl/mbx.sv
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Expand Up @@ -36,8 +36,7 @@ module mbx
output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o,
output top_racl_pkg::racl_error_log_t racl_error_o,
// Device port facing OpenTitan
input tlul_pkg::tl_h2d_t core_tl_d_i,
output tlul_pkg::tl_d2h_t core_tl_d_o,
Expand Down Expand Up @@ -246,8 +245,7 @@ module mbx
.read_data_i ( sysif_read_data ),
// RACL interface
.racl_policies_i ( racl_policies_i ),
.racl_error_o ( racl_error_o ),
.racl_error_log_o ( racl_error_log_o )
.racl_error_o ( racl_error_o )
);


Expand Down Expand Up @@ -375,6 +373,5 @@ module mbx
`ASSERT_KNOWN(SocTlAReadyKnownO_A, soc_tl_d_o.a_ready)
`ASSERT_KNOWN(SramTlAValidKnownO_A, sram_tl_h_o.a_valid)
`ASSERT_KNOWN(SramTlDReadyKnownO_A, sram_tl_h_o.d_ready)
`ASSERT_KNOWN(RaclErrorKnown_A, racl_error_o)
`ASSERT_KNOWN(RaclErrorLogKnown_A, racl_error_log_o)
`ASSERT_KNOWN(RaclErrorValidKnown_A, racl_error_o.valid)
endmodule
20 changes: 10 additions & 10 deletions hw/ip/mbx/rtl/mbx_soc_reg_top.sv
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Expand Up @@ -28,8 +28,7 @@ module mbx_soc_reg_top

// RACL interface
input top_racl_pkg::racl_policy_vec_t racl_policies_i,
output logic racl_error_o,
output top_racl_pkg::racl_error_log_t racl_error_log_o,
output top_racl_pkg::racl_error_log_t racl_error_o,

// Integrity check errors
output logic intg_err_o
Expand Down Expand Up @@ -174,7 +173,7 @@ module mbx_soc_reg_top
.busy_i (reg_busy),
.rdata_i (reg_rdata),
// Translate RACL error to TLUL error if enabled
.error_i (reg_error | (RaclErrorRsp & racl_error_o))
.error_i (reg_error | (RaclErrorRsp & racl_error_o.valid))
);

// cdc oversampling signals
Expand Down Expand Up @@ -520,16 +519,17 @@ module mbx_soc_reg_top

assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
// A valid address hit, access, but failed the RACL check
assign racl_error_o = |addr_hit & ((reg_re & ~|racl_addr_hit_read) |
(reg_we & ~|racl_addr_hit_write));
assign racl_error_log_o.racl_role = racl_role;
assign racl_error_o.valid = |addr_hit & ((reg_re & ~|racl_addr_hit_read) |
(reg_we & ~|racl_addr_hit_write));
assign racl_error_o.racl_role = racl_role;
assign racl_error_o.overflow = 1'b0;

if (EnableRacl) begin : gen_racl_log
assign racl_error_log_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
assign racl_error_log_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
assign racl_error_o.ctn_uid = top_racl_pkg::tlul_extract_ctn_uid_bits(tl_i.a_user.rsvd);
assign racl_error_o.read_access = tl_i.a_opcode == tlul_pkg::Get;
end else begin : gen_no_racl_log
assign racl_error_log_o.ctn_uid = '0;
assign racl_error_log_o.read_access = 1'b0;
assign racl_error_o.ctn_uid = '0;
assign racl_error_o.read_access = 1'b0;
end

// Check sub-word write is permitted
Expand Down
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