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Add classification functions #80
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Looks like aarch64 segfaulted during the travis build (not the test). No clue how that happened... |
That's... odd. This requires rebasing anyways, can you do that and see if it repros? |
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Looks like we do indeed have a particularly gribbly bug! |
I read somewhere that LLVM segfaults when an assert fails. When I run this in docker (I don't have access to an actual aarch64 machine) it succeeds, so I thought maybe we're running out of memory and a malloc assert is failing. |
I'm unclear why If we need to reduce codegen-units for this to build without crashing LLVM, and a user of the crate leads the codegen-units at the default quantity of 256 of 16, will their build explode when they use this crate? |
I read in an issue elsewhere that |
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I think I've figured out the issue, but I'm not sure what's really happening. The problem is the |
Following up from discussion: these two examples offer repro of our bug, but only when targeting aarch64, but seemingly only when generating tests, and only in release mode. #[test]
fn is_normal() {
assert!(core_simd::SimdF32::<64>::splat(0.).is_normal().to_array()[0]);
} #[test]
fn bug() {
use core_simd::{SimdF32, SimdU32};
let v = SimdF32::<64>::splat(0.);
let m = v.lanes_eq(SimdF32::splat(0.0)) & v.lanes_eq(SimdF32::splat(0.0));
assert!(m.to_array()[0]);
} |
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I reduced the maximum lane count from 64 to 32, since the error only occurred with 64-length vectors. This prevents AVX-512 vectors of |
Alright, looks like this is good now with that. Have you filed the LLVM bug somewhere? I think with that posted somewhere (anywhere) this can be merged. |
There's an LLVM bug filed (though I'm not 100% sure it's the same bug). I still need to file the rust and stdsimd bugs to track it. |
Filed #90 and rust-lang/rust#84020. |
Closes #36.