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Avoid using unexpected cfgs in user code #1667

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merged 3 commits into from
Nov 7, 2024
Merged

Avoid using unexpected cfgs in user code #1667

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5100670
Add ability to declare a feature without cfg checking
Urgau Nov 5, 2024
d25fa4e
Mark feature with missing corresponding target feature cfgs as such
Urgau Nov 5, 2024
ccff009
Add compile-time tests against unexpected target features cfgs
Urgau Nov 6, 2024
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1 change: 1 addition & 0 deletions crates/std_detect/src/detect/arch/aarch64.rs
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Expand Up @@ -160,6 +160,7 @@ features! {
@FEATURE: #[unstable(feature = "stdarch_aarch64_feature_detection", issue = "127764")] fp8fma: "fp8fma";
/// FEAT_FP8FMA (F8FMA Instructions)
@FEATURE: #[unstable(feature = "stdarch_aarch64_feature_detection", issue = "127764")] fpmr: "fpmr";
without cfg check: true;
/// FEAT_FPMR (Special-purpose AArch64-FPMR register)
@FEATURE: #[stable(feature = "simd_aarch64", since = "1.60.0")] frintts: "frintts";
/// FEAT_FRINTTS (float to integer rounding instructions)
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1 change: 1 addition & 0 deletions crates/std_detect/src/detect/arch/arm.rs
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Expand Up @@ -14,6 +14,7 @@ features! {
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] neon: "neon";
/// ARM Advanced SIMD (NEON) - Aarch32
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] pmull: "pmull";
without cfg check: true;
/// Polynomial Multiply
@FEATURE: #[unstable(feature = "stdarch_arm_feature_detection", issue = "111190")] crc: "crc";
/// CRC32 (Cyclic Redundancy Check)
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1 change: 1 addition & 0 deletions crates/std_detect/src/detect/arch/powerpc.rs
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Expand Up @@ -12,5 +12,6 @@ features! {
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] vsx: "vsx";
/// VSX
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] power8: "power8";
without cfg check: true;
/// Power8
}
1 change: 1 addition & 0 deletions crates/std_detect/src/detect/arch/powerpc64.rs
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Expand Up @@ -12,5 +12,6 @@ features! {
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] vsx: "vsx";
/// VSX
@FEATURE: #[unstable(feature = "stdarch_powerpc_feature_detection", issue = "111191")] power8: "power8";
without cfg check: true;
/// Power8
}
19 changes: 19 additions & 0 deletions crates/std_detect/src/detect/arch/riscv.rs
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Expand Up @@ -90,28 +90,36 @@ features! {
/// [ISA manual]: https://github.com/riscv/riscv-isa-manual/
#[stable(feature = "riscv_ratified", since = "1.76.0")]
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32i: "rv32i";
without cfg check: true;
/// RV32I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zifencei: "zifencei";
without cfg check: true;
/// "Zifencei" Instruction-Fetch Fence
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihintpause: "zihintpause";
without cfg check: true;
/// "Zihintpause" Pause Hint
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv64i: "rv64i";
without cfg check: true;
/// RV64I Base Integer Instruction Set
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] m: "m";
/// "M" Standard Extension for Integer Multiplication and Division
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] a: "a";
/// "A" Standard Extension for Atomic Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicsr: "zicsr";
without cfg check: true;
/// "Zicsr", Control and Status Register (CSR) Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zicntr: "zicntr";
without cfg check: true;
/// "Zicntr", Standard Extension for Base Counters and Timers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zihpm: "zihpm";
without cfg check: true;
/// "Zihpm", Standard Extension for Hardware Performance Counters
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] f: "f";
/// "F" Standard Extension for Single-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] d: "d";
/// "D" Standard Extension for Double-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] q: "q";
without cfg check: true;
/// "Q" Standard Extension for Quad-Precision Floating-Point
@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] c: "c";
/// "C" Standard Extension for Compressed Instructions
Expand All @@ -125,34 +133,45 @@ features! {
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zhinxmin: "zhinxmin";
/// "Zhinxmin" Standard Extension for Minimal Half-Precision Floating-Point in Integer Registers
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] ztso: "ztso";
without cfg check: true;
/// "Ztso" Standard Extension for Total Store Ordering

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv32e: "rv32e";
without cfg check: true;
/// RV32E Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] rv128i: "rv128i";
without cfg check: true;
/// RV128I Base Integer Instruction Set
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfh: "zfh";
/// "Zfh" Standard Extension for 16-Bit Half-Precision Floating-Point
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zfhmin: "zfhmin";
/// "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point Support
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] j: "j";
without cfg check: true;
/// "J" Standard Extension for Dynamically Translated Languages
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] p: "p";
without cfg check: true;
/// "P" Standard Extension for Packed-SIMD Instructions
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] v: "v";
/// "V" Standard Extension for Vector Operations
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] zam: "zam";
without cfg check: true;
/// "Zam" Standard Extension for Misaligned Atomics

@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] s: "s";
without cfg check: true;
/// Supervisor-Level ISA
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svnapot: "svnapot";
without cfg check: true;
/// "Svnapot" Standard Extension for NAPOT Translation Contiguity
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svpbmt: "svpbmt";
without cfg check: true;
/// "Svpbmt" Standard Extension for Page-Based Memory Types
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] svinval: "svinval";
without cfg check: true;
/// "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation
@FEATURE: #[unstable(feature = "stdarch_riscv_feature_detection", issue = "111192")] h: "h";
without cfg check: true;
/// Hypervisor Extension

@FEATURE: #[stable(feature = "riscv_ratified", since = "1.76.0")] zba: "zba";
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4 changes: 4 additions & 0 deletions crates/std_detect/src/detect/arch/x86.rs
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Expand Up @@ -123,8 +123,10 @@ features! {
@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] rdseed: "rdseed";
/// RDSEED
@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] tsc: "tsc";
without cfg check: true;
/// TSC (Time Stamp Counter)
@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] mmx: "mmx";
without cfg check: true;
/// MMX (MultiMedia eXtensions)
@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] sse: "sse";
/// SSE (Streaming SIMD Extensions)
Expand Down Expand Up @@ -157,8 +159,10 @@ features! {
@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512cd: "avx512cd" ;
/// AVX-512 CD (Conflict Detection Instructions)
@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512er: "avx512er";
without cfg check: true;
/// AVX-512 ER (Expo nential and Reciprocal Instructions)
@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512pf: "avx512pf";
without cfg check: true;
/// AVX-512 PF (Prefetch Instructions)
@FEATURE: #[stable(feature = "simd_x86", since = "1.27.0")] avx512bw: "avx512bw";
/// AVX-512 BW (Byte and Word Instructions)
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30 changes: 29 additions & 1 deletion crates/std_detect/src/detect/macros.rs
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Expand Up @@ -9,6 +9,24 @@ macro_rules! detect_feature {
$(cfg!(target_feature = $target_feature_lit) ||)*
$crate::detect::__is_feature_detected::$feature()
};
($feature:tt, $feature_lit:tt, without cfg check: true) => {
$crate::detect::__is_feature_detected::$feature()
};
}

#[allow(unused_macros, reason = "it's used in the features! macro below")]
macro_rules! check_cfg_feature {
($feature:tt, $feature_lit:tt) => {
check_cfg_feature!($feature, $feature_lit : $feature_lit)
};
($feature:tt, $feature_lit:tt : $($target_feature_lit:tt),*) => {
$(cfg!(target_feature = $target_feature_lit);)*
};
($feature:tt, $feature_lit:tt, without cfg check: $feature_cfg_check:literal) => {
// FIXME: Enable once rust-lang/rust#132577 hit's nightly
// #[expect(unexpected_cfgs, reason = $feature_lit)]
// { cfg!(target_feature = $feature_lit) }
};
}

#[allow(unused)]
Expand All @@ -21,6 +39,7 @@ macro_rules! features {
$(@BIND_FEATURE_NAME: $bind_feature:tt; $feature_impl:tt; $(#[$deprecate_attr:meta];)?)*
$(@NO_RUNTIME_DETECTION: $nort_feature:tt; )*
$(@FEATURE: #[$stability_attr:meta] $feature:ident: $feature_lit:tt;
$(without cfg check: $feature_cfg_check:literal;)?
$(implied by target_features: [$($target_feature_lit:tt),*];)?
$(#[$feature_comment:meta])*)*
) => {
Expand All @@ -32,7 +51,7 @@ macro_rules! features {
macro_rules! $macro_name {
$(
($feature_lit) => {
$crate::detect_feature!($feature, $feature_lit $(: $($target_feature_lit),*)?)
$crate::detect_feature!($feature, $feature_lit $(, without cfg check: $feature_cfg_check)? $(: $($target_feature_lit),*)?)
};
)*
$(
Expand Down Expand Up @@ -113,6 +132,15 @@ macro_rules! features {
};
}

#[test]
#[deny(unexpected_cfgs)]
#[deny(unfulfilled_lint_expectations)]
fn unexpected_cfgs() {
$(
check_cfg_feature!($feature, $feature_lit $(, without cfg check: $feature_cfg_check)? $(: $($target_feature_lit),*)?);
)*
}

/// Each variant denotes a position in a bitset for a particular feature.
///
/// PLEASE: do not use this, it is an implementation detail subject
Expand Down