0.2.1

Release Note

1. Avoided the timing fails by changing some connectivity in the module "spi_master" (commit 89f0a9d). Now the system working without timing fails. The reason why this works is unknown.

FreeBSD license.

0.2

Release note

1. Down the minimal version requirement of Vivado to 2015.4.
2. Changed the implementation of the gated clock in FPU, which results in better clock skew and shorter building time.
3. Fixed the bug in SD controller that causes the data in SD card corrupted after the system is booted. The SD card containing OS image can be reused now. Also, the change made in the system now can be kept.

OS image can be found on the release page of v0.1

Known Issue

1. The setup timing checks strangely failed on some paths in the L2 cache, where source code is intact. Those paths look like some false paths but have not sure. Even though having some timing fail, the system just works.
   (Details: #1)
   

Default IO Configuration

FreeBSD license.

0.1

Release note

All modifications are made based on the profile of Genesys2.

RTL modification:

1. Removed the Ethernet controller.
2. Changed the port configuration of UART boot to 576000 8N1.

Debian image modification:

1. Recompiled Linux kernel to remove the XILINX_EMACLITE driver which will cause boot stop when fail to detect the device.

Script modification:

1. Added ZC706 support for protosyn and pitonstream.
2. Changed the serial boot buad of pitonstream to 576000.

Pin arrangement

FreeBSD license.