> generate verilog

薛立伟 Linux tianyi-virtual-machine 6.5.0-15-generic OSCPU#15~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Fri Jan 12 18:54:30 UTC 2 x86_64 x86_64 x86_64 GNU/Linux 22:18:38 up 1:43, 1 user, load average: 1.08, 1.00, 0.86
wele0612 · Jan 30, 2024 · b9948fd · b9948fd
1 parent 8ba3dd2
commit b9948fd
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/npc/playground/src/Top_Module.scala b/npc/playground/src/Top_Module.scala
@@ -5,11 +5,15 @@ import chisel3._
   */
 class NVboard_IOs extends Bundle{
   val ledr=Output(Vec(16,Bool()))
+
+  def loadDefault():Unit={
+    ledr:=0.U.asTypeOf(io.ledr)
+  }
 }
 class Top_Module extends Module {
   val io=IO(new NVboard_IOs)
 
-  io.ledr:=0.U.asTypeOf(io.ledr)
+  io.loadDefault()
 
   io.ledr(0):=true.B
   io.ledr(1):=false.B